1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# Copyright (C) 2011-2012 3*4882a593Smuzhiyun# Gerald Kerma <dreagle@doukki.net> 4*4882a593Smuzhiyun# Simon Baatz <gmbnomis@gmail.com> 5*4882a593Smuzhiyun# Luka Perkov <luka@openwrt.org> 6*4882a593Smuzhiyun# 7*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun# 9*4882a593Smuzhiyun# Refer doc/README.kwbimage for more details about how-to configure 10*4882a593Smuzhiyun# and create kirkwood boot image 11*4882a593Smuzhiyun# 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun# Boot Media configurations 14*4882a593SmuzhiyunBOOT_FROM nand 15*4882a593SmuzhiyunNAND_ECC_MODE default 16*4882a593SmuzhiyunNAND_PAGE_SIZE 0x0800 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun# SOC registers configuration using bootrom header extension 19*4882a593Smuzhiyun# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun# Configure RGMII-0 interface pad voltage to 1.8V 22*4882a593SmuzhiyunDATA 0xffd100e0 0x1b1b1b9b 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun# Dram initalization for SINGLE x16 CL=5 @ 400MHz 25*4882a593SmuzhiyunDATA 0xffd01400 0x43000c30 # DDR Configuration register 26*4882a593Smuzhiyun# bit13-0: 0xc30, (3120 DDR2 clks refresh rate) 27*4882a593Smuzhiyun# bit23-14: 0x0, 28*4882a593Smuzhiyun# bit24: 0x1, enable exit self refresh mode on DDR access 29*4882a593Smuzhiyun# bit25: 0x1, required 30*4882a593Smuzhiyun# bit29-26: 0x0, 31*4882a593Smuzhiyun# bit31-30: 0x1, 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunDATA 0xffd01404 0x37543000 # DDR Controller Control Low 34*4882a593Smuzhiyun# bit4: 0x0, addr/cmd in smame cycle 35*4882a593Smuzhiyun# bit5: 0x0, clk is driven during self refresh, we don't care for APX 36*4882a593Smuzhiyun# bit6: 0x0, use recommended falling edge of clk for addr/cmd 37*4882a593Smuzhiyun# bit14: 0x0, input buffer always powered up 38*4882a593Smuzhiyun# bit18: 0x1, cpu lock transaction enabled 39*4882a593Smuzhiyun# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 40*4882a593Smuzhiyun# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 41*4882a593Smuzhiyun# bit30-28: 0x3, required 42*4882a593Smuzhiyun# bit31: 0x0, no additional STARTBURST delay 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunDATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 45*4882a593Smuzhiyun# bit3-0: TRAS lsbs 46*4882a593Smuzhiyun# bit7-4: TRCD 47*4882a593Smuzhiyun# bit11-8: TRP 48*4882a593Smuzhiyun# bit15-12: TWR 49*4882a593Smuzhiyun# bit19-16: TWTR 50*4882a593Smuzhiyun# bit20: TRAS msb 51*4882a593Smuzhiyun# bit23-21: 0x0 52*4882a593Smuzhiyun# bit27-24: TRRD 53*4882a593Smuzhiyun# bit31-28: TRTP 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunDATA 0xffd0140c 0x00000a33 # DDR Timing (High) 56*4882a593Smuzhiyun# bit6-0: TRFC 57*4882a593Smuzhiyun# bit8-7: TR2R 58*4882a593Smuzhiyun# bit10-9: TR2W 59*4882a593Smuzhiyun# bit12-11: TW2W 60*4882a593Smuzhiyun# bit31-13: 0x0, required 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunDATA 0xffd01410 0x0000000c # DDR Address Control 63*4882a593Smuzhiyun# bit1-0: 00, Cs0width (x8) 64*4882a593Smuzhiyun# bit3-2: 11, Cs0size (1Gb) 65*4882a593Smuzhiyun# bit5-4: 00, Cs1width (x8) 66*4882a593Smuzhiyun# bit7-6: 11, Cs1size (1Gb) 67*4882a593Smuzhiyun# bit9-8: 00, Cs2width (nonexistent) 68*4882a593Smuzhiyun# bit11-10: 00, Cs2size (nonexistent) 69*4882a593Smuzhiyun# bit13-12: 00, Cs3width (nonexistent) 70*4882a593Smuzhiyun# bit15-14: 00, Cs3size (nonexistent) 71*4882a593Smuzhiyun# bit16: 0, Cs0AddrSel 72*4882a593Smuzhiyun# bit17: 0, Cs1AddrSel 73*4882a593Smuzhiyun# bit18: 0, Cs2AddrSel 74*4882a593Smuzhiyun# bit19: 0, Cs3AddrSel 75*4882a593Smuzhiyun# bit31-20: 0x0, required 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunDATA 0xffd01414 0x00000000 # DDR Open Pages Control 78*4882a593Smuzhiyun# bit0: 0, OpenPage enabled 79*4882a593Smuzhiyun# bit31-1: 0x0, required 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunDATA 0xffd01418 0x00000000 # DDR Operation 82*4882a593Smuzhiyun# bit3-0: 0x0, DDR cmd 83*4882a593Smuzhiyun# bit31-4: 0x0, required 84*4882a593Smuzhiyun 85*4882a593SmuzhiyunDATA 0xffd0141c 0x00000c52 # DDR Mode 86*4882a593Smuzhiyun# bit2-0: 0x2, BurstLen=2 required 87*4882a593Smuzhiyun# bit3: 0x0, BurstType=0 required 88*4882a593Smuzhiyun# bit6-4: 0x4, CL=5 89*4882a593Smuzhiyun# bit7: 0x0, TestMode=0 normal 90*4882a593Smuzhiyun# bit8: 0x0, DLL reset=0 normal 91*4882a593Smuzhiyun# bit11-9: 0x6, auto-precharge write recovery 92*4882a593Smuzhiyun# bit12: 0x0, PD must be zero 93*4882a593Smuzhiyun# bit31-13: 0x0, required 94*4882a593Smuzhiyun 95*4882a593SmuzhiyunDATA 0xffd01420 0x00000040 # DDR Extended Mode 96*4882a593Smuzhiyun# bit0: 0, DDR DLL enabled 97*4882a593Smuzhiyun# bit1: 0, DDR drive strenght normal 98*4882a593Smuzhiyun# bit2: 1, DDR ODT control lsd (disabled) 99*4882a593Smuzhiyun# bit5-3: 0x0, required 100*4882a593Smuzhiyun# bit6: 0, DDR ODT control msb, (disabled) 101*4882a593Smuzhiyun# bit9-7: 0x0, required 102*4882a593Smuzhiyun# bit10: 0, differential DQS enabled 103*4882a593Smuzhiyun# bit11: 0, required 104*4882a593Smuzhiyun# bit12: 0, DDR output buffer enabled 105*4882a593Smuzhiyun# bit31-13: 0x0, required 106*4882a593Smuzhiyun 107*4882a593SmuzhiyunDATA 0xffd01424 0x0000f17f # DDR Controller Control High 108*4882a593Smuzhiyun# bit2-0: 0x7, required 109*4882a593Smuzhiyun# bit3: 0x1, MBUS Burst Chop disabled 110*4882a593Smuzhiyun# bit6-4: 0x7, required 111*4882a593Smuzhiyun# bit7: 0x0, 112*4882a593Smuzhiyun# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz 113*4882a593Smuzhiyun# bit9: 0x0, no half clock cycle addition to dataout 114*4882a593Smuzhiyun# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals 115*4882a593Smuzhiyun# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh 116*4882a593Smuzhiyun# bit15-12: 0xf, required 117*4882a593Smuzhiyun# bit31-16: 0, required 118*4882a593Smuzhiyun 119*4882a593SmuzhiyunDATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) 120*4882a593SmuzhiyunDATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) 121*4882a593Smuzhiyun 122*4882a593SmuzhiyunDATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 123*4882a593SmuzhiyunDATA 0xffd01504 0x0ffffff1 # CS[0]n Size 124*4882a593Smuzhiyun# bit0: 0x1, Window enabled 125*4882a593Smuzhiyun# bit1: 0x0, Write Protect disabled 126*4882a593Smuzhiyun# bit3-2: 0x0, CS0 hit selected 127*4882a593Smuzhiyun# bit23-4: 0xfffff, required 128*4882a593Smuzhiyun# bit31-24: 0x0f, Size (i.e. 256MB) 129*4882a593Smuzhiyun 130*4882a593SmuzhiyunDATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb 131*4882a593SmuzhiyunDATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled 132*4882a593Smuzhiyun 133*4882a593SmuzhiyunDATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled 134*4882a593SmuzhiyunDATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled 135*4882a593Smuzhiyun 136*4882a593SmuzhiyunDATA 0xffd01494 0x00030000 # DDR ODT Control (Low) 137*4882a593Smuzhiyun# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 138*4882a593Smuzhiyun# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 139*4882a593Smuzhiyun# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 140*4882a593Smuzhiyun# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 141*4882a593Smuzhiyun 142*4882a593SmuzhiyunDATA 0xffd01498 0x00000000 # DDR ODT Control (High) 143*4882a593Smuzhiyun# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above 144*4882a593Smuzhiyun# bit3-2: 0x1, ODT1 active NEVER! 145*4882a593Smuzhiyun# bit31-4: 0x0, required 146*4882a593Smuzhiyun 147*4882a593SmuzhiyunDATA 0xffd0149c 0x0000e803 # CPU ODT Control 148*4882a593SmuzhiyunDATA 0xffd01480 0x00000001 # DDR Initialization Control 149*4882a593Smuzhiyun# bit0: 0x1, enable DDR init upon this register write 150*4882a593Smuzhiyun 151*4882a593SmuzhiyunDATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register 152*4882a593SmuzhiyunDATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun# End of Header extension 155*4882a593SmuzhiyunDATA 0x0 0x0 156