Lines Matching refs:DDR

28 # DDR Configuration register
32 # bit24:    1, enable exit self refresh mode on DDR access
37 # DDR Controller Control Low
55 # DDR Timing (Low)
67 # DDR Timing (High)
75 # DDR Address Control
91 # DDR Open Pages Control
96 # DDR Operation
101 # DDR Mode
112 # DDR Extended Mode
125 # DDR Controller Control High
131 # bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
179 # DDR ODT Control (Low)
188 # DDR ODT Control (High)
202 # bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
207 # DDR Initialization Control
209 # bit0:     1, enable DDR init upon this register write