1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# Copyright (c) 2012 Michael Walle 3*4882a593Smuzhiyun# Michael Walle <michael@walle.cc> 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun# 7*4882a593Smuzhiyun# Refer doc/README.kwbimage for more details about how-to configure 8*4882a593Smuzhiyun# and create kirkwood boot image 9*4882a593Smuzhiyun# 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun# Boot Media configurations 12*4882a593SmuzhiyunBOOT_FROM spi 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun# SOC registers configuration using bootrom header extension 15*4882a593Smuzhiyun# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun# Configure RGMII-0/1 interface pad voltage to 1.8V 18*4882a593SmuzhiyunDATA 0xFFD100E0 0x1B1B9B9B 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun# L2 RAM Timing 0 21*4882a593SmuzhiyunDATA 0xFFD20134 0xBBBBBBBB 22*4882a593Smuzhiyun# not further specified in HW manual, timing taken from original vendor port 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun# L2 RAM Timing 1 25*4882a593SmuzhiyunDATA 0xFFD20138 0x00BBBBBB 26*4882a593Smuzhiyun# not further specified in HW manual, timing taken from original vendor port 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun# DDR Configuration register 29*4882a593SmuzhiyunDATA 0xFFD01400 0x43000618 30*4882a593Smuzhiyun# bit13-0: 0x618, 1560 DDR2 clks refresh rate 31*4882a593Smuzhiyun# bit23-14: 0 required 32*4882a593Smuzhiyun# bit24: 1, enable exit self refresh mode on DDR access 33*4882a593Smuzhiyun# bit25: 1 required 34*4882a593Smuzhiyun# bit29-26: 0 required 35*4882a593Smuzhiyun# bit31-30: 0b01 required 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun# DDR Controller Control Low 38*4882a593SmuzhiyunDATA 0xFFD01404 0x39543010 39*4882a593Smuzhiyun# bit3-0: 0 required 40*4882a593Smuzhiyun# bit4: 1, T2 mode, addr/cmd are driven for two cycles 41*4882a593Smuzhiyun# bit5: 0, clk is driven during self refresh, we don't care for APX 42*4882a593Smuzhiyun# bit6: 0, use recommended falling edge of clk for addr/cmd 43*4882a593Smuzhiyun# bit11-7: 0 required 44*4882a593Smuzhiyun# bit12: 1 required 45*4882a593Smuzhiyun# bit13: 1 required 46*4882a593Smuzhiyun# bit14: 0, input buffer always powered up 47*4882a593Smuzhiyun# bit17-15: 0 required 48*4882a593Smuzhiyun# bit18: 1, cpu lock transaction enabled 49*4882a593Smuzhiyun# bit19: 0 required 50*4882a593Smuzhiyun# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 51*4882a593Smuzhiyun# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 52*4882a593Smuzhiyun# bit30-28: 3 required 53*4882a593Smuzhiyun# bit31: 0, no additional STARTBURST delay 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun# DDR Timing (Low) 56*4882a593SmuzhiyunDATA 0xFFD01408 0x22125441 57*4882a593Smuzhiyun# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0]) 58*4882a593Smuzhiyun# bit7-4: 4, 5 cycle tRCD 59*4882a593Smuzhiyun# bit11-8: 4, 5 cyle tRP 60*4882a593Smuzhiyun# bit15-12: 5, 6 cyle tWR 61*4882a593Smuzhiyun# bit19-16: 2, 3 cyle tWTR 62*4882a593Smuzhiyun# bit20: 1, 18 cycle tRAS (tRAS[4]) 63*4882a593Smuzhiyun# bit23-21: 0 required 64*4882a593Smuzhiyun# bit27-24: 2, 3 cycle tRRD 65*4882a593Smuzhiyun# bit31-28: 2, 3 cyle tRTP 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun# DDR Timing (High) 68*4882a593SmuzhiyunDATA 0xFFD0140C 0x00000832 69*4882a593Smuzhiyun# bit6-0: 0x32, 50 cycle tRFC 70*4882a593Smuzhiyun# bit8-7: 0, 1 cycle tR2R 71*4882a593Smuzhiyun# bit10-9: 0, 1 cyle tR2W 72*4882a593Smuzhiyun# bit12-11: 1, 2 cylce tW2W 73*4882a593Smuzhiyun# bit31-13: 0 required 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun# DDR Address Control 76*4882a593SmuzhiyunDATA 0xFFD01410 0x0000000C 77*4882a593Smuzhiyun# bit1-0: 0, Cs0width=x8 78*4882a593Smuzhiyun# bit3-2: 3, Cs0size=1Gbit 79*4882a593Smuzhiyun# bit5-4: 0, Cs1width=nonexistent 80*4882a593Smuzhiyun# bit7-6: 0, Cs1size=nonexistent 81*4882a593Smuzhiyun# bit9-8: 0, Cs2width=nonexistent 82*4882a593Smuzhiyun# bit11-10: 0, Cs2size=nonexistent 83*4882a593Smuzhiyun# bit13-12: 0, Cs3width=nonexistent 84*4882a593Smuzhiyun# bit15-14: 0, Cs3size=nonexistent 85*4882a593Smuzhiyun# bit16: 0, Cs0AddrSel 86*4882a593Smuzhiyun# bit17: 0, Cs1AddrSel 87*4882a593Smuzhiyun# bit18: 0, Cs2AddrSel 88*4882a593Smuzhiyun# bit19: 0, Cs3AddrSel 89*4882a593Smuzhiyun# bit31-20: 0 required 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun# DDR Open Pages Control 92*4882a593SmuzhiyunDATA 0xFFD01414 0x00000000 93*4882a593Smuzhiyun# bit0: 0, OPEn=OpenPage enabled 94*4882a593Smuzhiyun# bit31-1: 0 required 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun# DDR Operation 97*4882a593SmuzhiyunDATA 0xFFD01418 0x00000000 98*4882a593Smuzhiyun# bit3-0: 0, Cmd=Normal SDRAM Mode 99*4882a593Smuzhiyun# bit31-4: 0 required 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun# DDR Mode 102*4882a593SmuzhiyunDATA 0xFFD0141C 0x00000652 103*4882a593Smuzhiyun# bit2-0: 2, Burst Length (2 required) 104*4882a593Smuzhiyun# bit3: 0, Burst Type (0 required) 105*4882a593Smuzhiyun# bit6-4: 5, CAS Latency (CL) 5 106*4882a593Smuzhiyun# bit7: 0, (Test Mode) Normal operation 107*4882a593Smuzhiyun# bit8: 0, (Reset DLL) Normal operation 108*4882a593Smuzhiyun# bit11-9: 3, Write recovery for auto-precharge (3 required) 109*4882a593Smuzhiyun# bit12: 0, Fast Active power down exit time (0 required) 110*4882a593Smuzhiyun# bit31-13: 0 required 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun# DDR Extended Mode 113*4882a593SmuzhiyunDATA 0xFFD01420 0x00000006 114*4882a593Smuzhiyun# bit0: 0, DRAM DLL enabled 115*4882a593Smuzhiyun# bit1: 1, DRAM drive strength reduced 116*4882a593Smuzhiyun# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination) 117*4882a593Smuzhiyun# bit5-3: 0 required 118*4882a593Smuzhiyun# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination) 119*4882a593Smuzhiyun# bit9-7: 0 required 120*4882a593Smuzhiyun# bit10: 0, differential DQS enabled 121*4882a593Smuzhiyun# bit11: 0 required 122*4882a593Smuzhiyun# bit12: 0, DRAM output buffer enabled 123*4882a593Smuzhiyun# bit31-13: 0 required 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun# DDR Controller Control High 126*4882a593SmuzhiyunDATA 0xFFD01424 0x0000F17F 127*4882a593Smuzhiyun# bit2-0: 0x7 required 128*4882a593Smuzhiyun# bit3: 1, MBUS Burst Chop disabled 129*4882a593Smuzhiyun# bit6-4: 0x7 required 130*4882a593Smuzhiyun# bit7: 0 required (???) 131*4882a593Smuzhiyun# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz 132*4882a593Smuzhiyun# bit9: 0, no half clock cycle addition to dataout 133*4882a593Smuzhiyun# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 134*4882a593Smuzhiyun# bit11: 0, 1/4 clock cycle skew disabled for write mesh 135*4882a593Smuzhiyun# bit15-12: 0xf required 136*4882a593Smuzhiyun# bit31-16: 0 required 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun# DDR2 ODT Read Timing (default values) 139*4882a593SmuzhiyunDATA 0xFFD01428 0x00085520 140*4882a593Smuzhiyun# bit3-0: 0 required 141*4882a593Smuzhiyun# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal 142*4882a593Smuzhiyun# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal 143*4882a593Smuzhiyun# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal 144*4882a593Smuzhiyun# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 145*4882a593Smuzhiyun# bit31-20: 0 required 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun# DDR2 ODT Write Timing (default values) 148*4882a593SmuzhiyunDATA 0xFFD0147C 0x00008552 149*4882a593Smuzhiyun# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal 150*4882a593Smuzhiyun# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal 151*4882a593Smuzhiyun# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal 152*4882a593Smuzhiyun# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 153*4882a593Smuzhiyun# bit31-16: 0 required 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun# CS[0]n Base address 156*4882a593SmuzhiyunDATA 0xFFD01500 0x00000000 157*4882a593Smuzhiyun# at 0x0 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun# CS[0]n Size 160*4882a593SmuzhiyunDATA 0xFFD01504 0x0FFFFFF1 161*4882a593Smuzhiyun# bit0: 1, Window enabled 162*4882a593Smuzhiyun# bit1: 0, Write Protect disabled 163*4882a593Smuzhiyun# bit3-2: 0x0, CS0 hit selected 164*4882a593Smuzhiyun# bit23-4: 0xfffff required 165*4882a593Smuzhiyun# bit31-24: 0x0f, Size (i.e. 256MB) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun# CS[1]n Size 168*4882a593SmuzhiyunDATA 0xFFD0150C 0x00000000 169*4882a593Smuzhiyun# window disabled 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun# CS[2]n Size 172*4882a593SmuzhiyunDATA 0xFFD01514 0x00000000 173*4882a593Smuzhiyun# window disabled 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun# CS[3]n Size 176*4882a593SmuzhiyunDATA 0xFFD0151C 0x00000000 177*4882a593Smuzhiyun# window disabled 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun# DDR ODT Control (Low) 180*4882a593SmuzhiyunDATA 0xFFD01494 0x00010000 181*4882a593Smuzhiyun# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM 182*4882a593Smuzhiyun# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM 183*4882a593Smuzhiyun# bit15-8: 0 required 184*4882a593Smuzhiyun# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0 185*4882a593Smuzhiyun# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM 186*4882a593Smuzhiyun# bit31-24: 0 required 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun# DDR ODT Control (High) 189*4882a593SmuzhiyunDATA 0xFFD01498 0x00000000 190*4882a593Smuzhiyun# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register 191*4882a593Smuzhiyun# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register 192*4882a593Smuzhiyun# bit31-4 0 required 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun# CPU ODT Control 195*4882a593SmuzhiyunDATA 0xFFD0149C 0x0000E80F 196*4882a593Smuzhiyun# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 197*4882a593Smuzhiyun# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 198*4882a593Smuzhiyun# bit9-8: 0, Internal ODT assertion is controlled by fiels 199*4882a593Smuzhiyun# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm 200*4882a593Smuzhiyun# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm 201*4882a593Smuzhiyun# bit14: 1, M_STARTBURST_IN ODT enabled 202*4882a593Smuzhiyun# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values 203*4882a593Smuzhiyun# bit20-16: 0, Pad N channel driving strength for ODT 204*4882a593Smuzhiyun# bit25-21: 0, Pad P channel driving strength for ODT 205*4882a593Smuzhiyun# bit31-26: 0 required 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun# DDR Initialization Control 208*4882a593SmuzhiyunDATA 0xFFD01480 0x00000001 209*4882a593Smuzhiyun# bit0: 1, enable DDR init upon this register write 210*4882a593Smuzhiyun# bit31-1: 0, required 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun# End of Header extension 213*4882a593SmuzhiyunDATA 0x0 0x0 214