Lines Matching refs:DDR

28 DATA 0xFFD01400 0x43000c30	# DDR Configuration register
31 # bit24: 1= enable exit self refresh mode on DDR access
36 DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
47 DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
58 DATA 0xFFD0140C 0x00000833	#  DDR Timing (High)
65 DATA 0xFFD01410 0x0000000d	#  DDR Address Control
80 DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
84 DATA 0xFFD01418 0x00000000	#  DDR Operation
85 # bit3-0:   0x0, DDR cmd
88 DATA 0xFFD0141C 0x00000C52	#  DDR Mode
98 DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
99 # bit0:    0,  DDR DLL enabled
100 # bit1:    0,  DDR drive strenght normal
101 # bit2:    0,  DDR ODT control lsd (disabled)
103 # bit6:    1,  DDR ODT control msb, (disabled)
107 # bit12:   0, DDR output buffer enabled
110 DATA 0xFFD01424 0x0000F1FF	#  DDR Controller Control High
115 # bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
141 DATA 0xFFD01494 0x003C0000	#  DDR ODT Control (Low)
142 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
148 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
149 #bit0=1, enable DDR init upon this register write