Lines Matching refs:DDR
24 DATA 0xffd01400 0x43000c30 # DDR Configuration register
27 # bit24: 0x1, enable exit self refresh mode on DDR access
32 DATA 0xffd01404 0x37543000 # DDR Controller Control Low
43 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
54 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
61 DATA 0xffd01410 0x000000cc # DDR Address Control
76 DATA 0xffd01414 0x00000000 # DDR Open Pages Control
80 DATA 0xffd01418 0x00000000 # DDR Operation
81 # bit3-0: 0x0, DDR cmd
84 DATA 0xffd0141c 0x00000c52 # DDR Mode
94 DATA 0xffd01420 0x00000040 # DDR Extended Mode
95 # bit0: 0, DDR DLL enabled
96 # bit1: 0, DDR drive strenght normal
97 # bit2: 0, DDR ODT control lsd (disabled)
99 # bit6: 1, DDR ODT control msb, (disabled)
103 # bit12: 0, DDR output buffer enabled
106 DATA 0xffd01424 0x0000f17f # DDR Controller Control High
111 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
135 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
141 DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
147 DATA 0xffd01480 0x00000001 # DDR Initialization Control
148 # bit0: 0x1, enable DDR init upon this register write