Lines Matching refs:DDR
47 # bit24: 1= enable exit self refresh mode on DDR access
52 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
64 DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
75 DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
82 DATA 0xFFD01410 0x0000000D # DDR Address Control
97 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
101 DATA 0xFFD01418 0x00000000 # DDR Operation
102 # bit3-0: 0x0, DDR cmd
105 DATA 0xFFD0141C 0x00000652 # DDR Mode
106 DATA 0xFFD01420 0x00000044 # DDR Extended Mode
107 # bit0: 0, DDR DLL enabled
108 # bit1: 0, DDR drive strenght normal
109 # bit2: 1, DDR ODT control lsd disabled
111 # bit6: 1, DDR ODT control msb, enabled
115 # bit12: 0, DDR output buffer enabled
118 DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
144 DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
148 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
159 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
160 # bit0=1, enable DDR init upon this register write