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Searched refs:CLK_TOP_SPI_SEL (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dspi-mt65xx.txt33 The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
60 <&topckgen CLK_TOP_SPI_SEL>,
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt8135-clk.h87 #define CLK_TOP_SPI_SEL 76 macro
H A Dmt8516-clk.h189 #define CLK_TOP_SPI_SEL 157 macro
H A Dmt6765-clk.h142 #define CLK_TOP_SPI_SEL 107 macro
H A Dmt8173-clk.h102 #define CLK_TOP_SPI_SEL 92 macro
H A Dmt2712-clk.h139 #define CLK_TOP_SPI_SEL 108 macro
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi555 <&topckgen CLK_TOP_SPI_SEL>,
634 <&topckgen CLK_TOP_SPI_SEL>,
647 <&topckgen CLK_TOP_SPI_SEL>,
660 <&topckgen CLK_TOP_SPI_SEL>,
673 <&topckgen CLK_TOP_SPI_SEL>,
H A Dmt8516.dtsi370 <&topckgen CLK_TOP_SPI_SEL>,
H A Dmt8173.dtsi704 <&topckgen CLK_TOP_SPI_SEL>,
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt8135.c372 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
H A Dclk-mt8516.c421 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
H A Dclk-mt8167.c611 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
H A Dclk-mt8173.c554 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
H A Dclk-mt6765.c402 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
H A Dclk-mt2712.c758 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",