1*4882a593SmuzhiyunBinding for MTK SPI controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should be one of the following. 5*4882a593Smuzhiyun - mediatek,mt2701-spi: for mt2701 platforms 6*4882a593Smuzhiyun - mediatek,mt2712-spi: for mt2712 platforms 7*4882a593Smuzhiyun - mediatek,mt6589-spi: for mt6589 platforms 8*4882a593Smuzhiyun - mediatek,mt6765-spi: for mt6765 platforms 9*4882a593Smuzhiyun - mediatek,mt7622-spi: for mt7622 platforms 10*4882a593Smuzhiyun - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms 11*4882a593Smuzhiyun - mediatek,mt8135-spi: for mt8135 platforms 12*4882a593Smuzhiyun - mediatek,mt8173-spi: for mt8173 platforms 13*4882a593Smuzhiyun - mediatek,mt8183-spi: for mt8183 platforms 14*4882a593Smuzhiyun - "mediatek,mt8192-spi", "mediatek,mt6765-spi": for mt8192 platforms 15*4882a593Smuzhiyun - "mediatek,mt8516-spi", "mediatek,mt2712-spi": for mt8516 platforms 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- #address-cells: should be 1. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- #size-cells: should be 0. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- reg: Address and length of the register set for the device 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- interrupts: Should contain spi interrupt 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- clocks: phandles to input clocks. 26*4882a593Smuzhiyun The first should be one of the following. It's PLL. 27*4882a593Smuzhiyun - <&clk26m>: specify parent clock 26MHZ. 28*4882a593Smuzhiyun - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ. 29*4882a593Smuzhiyun It's the default one. 30*4882a593Smuzhiyun - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ. 31*4882a593Smuzhiyun - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. 32*4882a593Smuzhiyun - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. 33*4882a593Smuzhiyun The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux. 34*4882a593Smuzhiyun The third is <&pericfg CLK_PERI_SPI0>. It's clock gate. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun- clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the 37*4882a593Smuzhiyun muxes clock, and "spi-clk" for the clock gate. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunOptional properties: 40*4882a593Smuzhiyun-cs-gpios: see spi-bus.txt. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi 43*4882a593Smuzhiyun controller used. This is an array, the element value should be 0~3, 44*4882a593Smuzhiyun only required for MT8173. 45*4882a593Smuzhiyun 0: specify GPIO69,70,71,72 for spi pins. 46*4882a593Smuzhiyun 1: specify GPIO102,103,104,105 for spi pins. 47*4882a593Smuzhiyun 2: specify GPIO128,129,130,131 for spi pins. 48*4882a593Smuzhiyun 3: specify GPIO5,6,7,8 for spi pins. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunExample: 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun- SoC Specific Portion: 53*4882a593Smuzhiyunspi: spi@1100a000 { 54*4882a593Smuzhiyun compatible = "mediatek,mt8173-spi"; 55*4882a593Smuzhiyun #address-cells = <1>; 56*4882a593Smuzhiyun #size-cells = <0>; 57*4882a593Smuzhiyun reg = <0 0x1100a000 0 0x1000>; 58*4882a593Smuzhiyun interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 59*4882a593Smuzhiyun clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 60*4882a593Smuzhiyun <&topckgen CLK_TOP_SPI_SEL>, 61*4882a593Smuzhiyun <&pericfg CLK_PERI_SPI0>; 62*4882a593Smuzhiyun clock-names = "parent-clk", "sel-clk", "spi-clk"; 63*4882a593Smuzhiyun cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; 64*4882a593Smuzhiyun mediatek,pad-select = <1>, <0>; 65*4882a593Smuzhiyun}; 66