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Searched refs:CLK_TOP_MSDC30_1_SEL (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt8135-clk.h81 #define CLK_TOP_MSDC30_1_SEL 70 macro
H A Dmt7629-clk.h96 #define CLK_TOP_MSDC30_1_SEL 86 macro
H A Dmt7622-clk.h81 #define CLK_TOP_MSDC30_1_SEL 69 macro
H A Dmt6765-clk.h145 #define CLK_TOP_MSDC30_1_SEL 110 macro
H A Dmt8173-clk.h107 #define CLK_TOP_MSDC30_1_SEL 97 macro
H A Dmt2712-clk.h144 #define CLK_TOP_MSDC30_1_SEL 113 macro
H A Dmt2701-clk.h102 #define CLK_TOP_MSDC30_1_SEL 91 macro
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt8135.c364 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
H A Dclk-mt7629.c516 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
H A Dclk-mt7622.c547 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
H A Dclk-mt2701.c515 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
H A Dclk-mt8173.c560 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
H A Dclk-mt6765.c412 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
H A Dclk-mt2712.c769 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt7622-rfb1.dts216 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
H A Dmt7622-bananapi-bpi-r64.dts239 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmt7623.dtsi700 <&topckgen CLK_TOP_MSDC30_1_SEL>;