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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP)
10 VOP (Video Output Processor) is the display controller for the Rockchip
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
[all …]
H A Drockchip-rgb.txt5 - compatible: matching the soc type:
6 - "rockchip,px30-rgb";
7 - "rockchip,rk1808-rgb";
8 - "rockchip,rk3066-rgb";
9 - "rockchip,rk3128-rgb";
10 - "rockchip,rk3288-rgb";
11 - "rockchip,rk3308-rgb";
12 - "rockchip,rk3368-rgb";
13 - "rockchip,rv1108-rgb";
14 - "rockchip,rv1126-rgb";
[all …]
H A Drockchip-lvds.txt1 Rockchip RK3288 LVDS interface
5 - compatible: matching the soc type, one of
6 - "rockchip,rk3288-lvds";
7 - "rockchip,px30-lvds";
9 - reg: physical base address of the controller and length
11 - clocks: must include clock specifiers corresponding to entries in the
12 clock-names property.
13 - clock-names: must contain "pclk_lvds"
15 - avdd1v0-supply: regulator phandle for 1.0V analog power
16 - avdd1v8-supply: regulator phandle for 1.8V analog power
[all …]
H A Danalogix_dp-rockchip.txt1 Rockchip RK3288 specific extensions to the Analogix Display Port
5 - compatible: "rockchip,rk3288-dp",
6 "rockchip,rk3399-edp";
8 - reg: physical base address of the controller and length
10 - clocks: from common clock binding: handle to dp clock.
13 - clock-names: from common clock binding:
16 - resets: Must contain an entry for each entry in reset-names.
19 - pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
20 - pinctrl-0: pin-control mode. should be <&edp_hpd>
22 - reset-names: Must include the name "dp"
[all …]
H A Ddw_mipi_dsi_rockchip.txt5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 - reg: Represent the physical address range of the controller.
12 - interrupts: Represent the controller's interrupt to the CPU(s).
13 - clocks, clock-names: Phandles to the controller's pll reference
17 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
29 debug node: /d/dri/0/ff900000.vop/vop_dump/dump
30 cat /d/dri/0/ff900000.vop/vop_dump/dump get more help
31 the upper ff900000.vop is different at different SOC platform.
45 bool "Rockchip VOP driver"
52 This selects support for the VOP driver.If you want to
53 enable VOP on Rockchip SoC, you should select this option.
67 on RK3288 or RK3399 based SoC, you should select this option.
89 enable HDMI on RK3288 or RK3399 based SoC, you should select
98 enable MIPI DSI on RK3288 or RK3399 based SoC, you should
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pwm/
H A Dpwm-rockchip.txt4 - compatible: should be "rockchip,<name>-pwm"
5 "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
6 "rockchip,rk3288-pwm": found on RK3288 SOC
7 "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC
8 "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
9 - reg: physical base address and length of the controller's registers
10 - clocks: See ../clock/clock-bindings.txt
11 - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
12 - There is one clock that's used both to derive the functional clock
14 - For newer hardware (rk3328 and future socs): specified by name
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip_crtc.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
25 { .compatible = "rockchip-vp" },
30 .name = "rockchip-vp",
137 .compatible = "rockchip,rk3036-vop",
140 .compatible = "rockchip,rv1108-vop",
143 .compatible = "rockchip,rv1106-vop",
146 .compatible = "rockchip,rv1126-vop",
149 .compatible = "rockchip,rk3126-vop",
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk3288_vop.c6 * SPDX-License-Identifier: GPL-2.0+
27 struct rk3288_vop *regs = priv->regs; in rk3288_set_pin_polarity()
29 /* The RK3328 VOP (v3.1) has its polarity configuration in ctrl0 */ in rk3288_set_pin_polarity()
30 clrsetbits_le32(&regs->dsp_ctrl0, in rk3288_set_pin_polarity()
40 /* lcdc(vop) iodomain select 1.8V */ in rk3288_set_io_vsel()
41 rk_setreg(&grf->io_vsel, 1 << 0); in rk3288_set_io_vsel()
60 if (!(gd->flags & GD_FLG_RELOC)) in rk3288_vop_probe()
63 /* Set the LCDC(vop) iodomain to 1.8V */ in rk3288_vop_probe()
66 /* Probe regulators required for the RK3288 VOP */ in rk3288_vop_probe()
76 struct rk3288_vop *regs = priv->regs; in rk_vop_remove()
[all …]
H A Drk3288_hdmi.c4 * SPDX-License-Identifier: GPL-2.0+
28 int vop_id = uc_plat->source_id; in rk3288_hdmi_enable()
29 struct rk3288_grf *grf = priv->grf; in rk3288_hdmi_enable()
32 rk_setreg(&grf->soc_con6, 1 << 15); in rk3288_hdmi_enable()
34 /* hdmi data from vop id */ in rk3288_hdmi_enable()
35 rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0); in rk3288_hdmi_enable()
43 struct dw_hdmi *hdmi = &priv->hdmi; in rk3288_hdmi_ofdata_to_platdata()
45 hdmi->i2c_clk_high = 0x7a; in rk3288_hdmi_ofdata_to_platdata()
46 hdmi->i2c_clk_low = 0x8d; in rk3288_hdmi_ofdata_to_platdata()
49 * TODO(sjg@chromium.org): The above values don't work - these in rk3288_hdmi_ofdata_to_platdata()
[all …]
H A DKconfig6 # display by configure the device tree, and the vop driver will do the rest.
8 # Author: Eric Gao <eric.gao@rock-chips.com>
15 Rockchip SoCs provide video output capabilities for High-Definition
16 Multimedia Interface (HDMI), Low-voltage Differential Signalling
19 This driver supports the on-chip video output device, and targets the
20 Rockchip RK3288 and RK3399.
29 framebuffer during device-model binding/probing.
38 framebuffer during device-model binding/probing.
52 This enables Low-voltage Differential Signaling(LVDS) display
60 This enables High-Definition Multimedia Interface display support.
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/video/
H A Drockchip_lcdc.txt1 Device-Tree bindings for Rockchip SoC display controller (VOP / LCDC)
2 VOP (Video Output Process) / LCDC is the Display Controller for the
7 - compatible: value should be one of the following
8 "rockchip,rk3288-lcdc"; /* for RK3288 SoCs */
9 "rockchip,rk3368-lcdc"; /* for RK3368 SoCs */
10 "rockchip,rk322x-lcdc"; /* for RK322X SoCs */
11 "rockchip,rk3399-lcdc"; /* for RK3399 SoCs */
12 - rockchip,prop: set the lcdc as primary or extend display.
13 - rochchip,pwr18: set the controller IO voltage,0 is 3.3v,1 is 1.8v.
14 - reg: physical base address and length of the LCDC registers set.
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3288.dtsi2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/video/rk3288.h>
16 compatible = "rockchip,rk3288";
[all …]
H A D.rk3288-rock2-square.dtb.dts.tmp
H A D.rk3288-vyasa.dtb.dts.tmp
H A Drk3128.dtsi4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rk3128-cru.h>
12 #include <dt-bindings/media/rockchip_mipi_dsi.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
H A D.rk3288-evb.dtb.dts.tmp
H A D.rk3288-popmetal.dtb.dts.tmp
H A D.rk3288-fennec.dtb.dts.tmp
H A D.rk3288-tinker.dtb.dts.tmp
H A D.rk3288-firefly.dtb.dts.tmp
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/suspend/rockchip-rk3288.h>
[all …]
H A Drk3288-linux.dtsi4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT).
6 #include <dt-bindings/soc/rockchip-system-status.h>
7 #include "rk3288-dram-default-timing.dtsi"
11 …250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 …
14 /delete-node/ dmc@ff610000;
17 compatible = "rockchip,rk3288-dfi";
24 compatible = "rockchip,rk3288-dmc";
25 devfreq-events = <&dfi>;
29 clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0",
33 operating-points-v2 = <&dmc_opp_table>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3288/
H A Drk3288.c4 * SPDX-License-Identifier: GPL-2.0+
23 #include <dt-bindings/clock/rk3288-cru.h>
75 rk_setreg(&grf->soc_con2, 1 << 0); in arch_cpu_init()
78 rk_setreg(&grf->soc_con7, 1 << 15); in arch_cpu_init()
87 /* Set vop qos to highest priority */ in arch_cpu_init()
99 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | in board_debug_uart_init()
178 /* set vop qos to higher priority */ in rk3288_qos_init()
182 if (!fdt_node_check_compatible(gd->fdt_blob, 0, in rk3288_qos_init()
183 "rockchip,rk3288-tinker")) in rk3288_qos_init()
201 switch (cru->cru_glb_rst_st) { in rk3288_detect_reset_reason()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/
H A Drockchip-io-domain.txt2 -------------------------------------
8 A specific example using rk3288:
9 - If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
18 - any logic for deciding what voltage we should set regulators to
19 - any logic for deciding whether regulators (or internal SoC blocks)
33 - compatible: should be one of:
34 - "rockchip,px30-io-voltage-domain" for px30
35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
36 - "rockchip,rk3188-io-voltage-domain" for rk3188
37 - "rockchip,rk3228-io-voltage-domain" for rk3228
[all …]

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