1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <clk.h>
9*4882a593Smuzhiyun #include <display.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <dw_hdmi.h>
12*4882a593Smuzhiyun #include <edid.h>
13*4882a593Smuzhiyun #include <regmap.h>
14*4882a593Smuzhiyun #include <syscon.h>
15*4882a593Smuzhiyun #include <asm/gpio.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <asm/arch/clock.h>
18*4882a593Smuzhiyun #include <asm/arch/hardware.h>
19*4882a593Smuzhiyun #include <asm/arch/grf_rk3288.h>
20*4882a593Smuzhiyun #include <power/regulator.h>
21*4882a593Smuzhiyun #include "rk_hdmi.h"
22*4882a593Smuzhiyun
rk3288_hdmi_enable(struct udevice * dev,int panel_bpp,const struct display_timing * edid)23*4882a593Smuzhiyun static int rk3288_hdmi_enable(struct udevice *dev, int panel_bpp,
24*4882a593Smuzhiyun const struct display_timing *edid)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct rk_hdmi_priv *priv = dev_get_priv(dev);
27*4882a593Smuzhiyun struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
28*4882a593Smuzhiyun int vop_id = uc_plat->source_id;
29*4882a593Smuzhiyun struct rk3288_grf *grf = priv->grf;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* hdmi source select hdmi controller */
32*4882a593Smuzhiyun rk_setreg(&grf->soc_con6, 1 << 15);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* hdmi data from vop id */
35*4882a593Smuzhiyun rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
rk3288_hdmi_ofdata_to_platdata(struct udevice * dev)40*4882a593Smuzhiyun static int rk3288_hdmi_ofdata_to_platdata(struct udevice *dev)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct rk_hdmi_priv *priv = dev_get_priv(dev);
43*4882a593Smuzhiyun struct dw_hdmi *hdmi = &priv->hdmi;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun hdmi->i2c_clk_high = 0x7a;
46*4882a593Smuzhiyun hdmi->i2c_clk_low = 0x8d;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * TODO(sjg@chromium.org): The above values don't work - these
50*4882a593Smuzhiyun * ones work better, but generate lots of errors in the data.
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun hdmi->i2c_clk_high = 0x0d;
53*4882a593Smuzhiyun hdmi->i2c_clk_low = 0x0d;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun return rk_hdmi_ofdata_to_platdata(dev);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
rk3288_clk_config(struct udevice * dev)58*4882a593Smuzhiyun static int rk3288_clk_config(struct udevice *dev)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
61*4882a593Smuzhiyun struct clk clk;
62*4882a593Smuzhiyun int ret;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * Configure the maximum clock to permit whatever resolution the
66*4882a593Smuzhiyun * monitor wants
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
69*4882a593Smuzhiyun if (ret >= 0) {
70*4882a593Smuzhiyun ret = clk_set_rate(&clk, 384000000);
71*4882a593Smuzhiyun clk_free(&clk);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun if (ret < 0) {
74*4882a593Smuzhiyun debug("%s: Failed to set clock in source device '%s': ret=%d\n",
75*4882a593Smuzhiyun __func__, uc_plat->src_dev->name, ret);
76*4882a593Smuzhiyun return ret;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const char * const rk3288_regulator_names[] = {
83*4882a593Smuzhiyun "vcc50_hdmi"
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
rk3288_hdmi_probe(struct udevice * dev)86*4882a593Smuzhiyun static int rk3288_hdmi_probe(struct udevice *dev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun /* Enable VOP clock for RK3288 */
89*4882a593Smuzhiyun rk3288_clk_config(dev);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Enable regulators required for HDMI */
92*4882a593Smuzhiyun rk_hdmi_probe_regulators(dev, rk3288_regulator_names,
93*4882a593Smuzhiyun ARRAY_SIZE(rk3288_regulator_names));
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return rk_hdmi_probe(dev);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static const struct dm_display_ops rk3288_hdmi_ops = {
99*4882a593Smuzhiyun .read_edid = rk_hdmi_read_edid,
100*4882a593Smuzhiyun .enable = rk3288_hdmi_enable,
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct udevice_id rk3288_hdmi_ids[] = {
104*4882a593Smuzhiyun { .compatible = "rockchip,rk3288-dw-hdmi" },
105*4882a593Smuzhiyun { }
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun U_BOOT_DRIVER(rk3288_hdmi_rockchip) = {
109*4882a593Smuzhiyun .name = "rk3288_hdmi_rockchip",
110*4882a593Smuzhiyun .id = UCLASS_DISPLAY,
111*4882a593Smuzhiyun .of_match = rk3288_hdmi_ids,
112*4882a593Smuzhiyun .ops = &rk3288_hdmi_ops,
113*4882a593Smuzhiyun .ofdata_to_platdata = rk3288_hdmi_ofdata_to_platdata,
114*4882a593Smuzhiyun .probe = rk3288_hdmi_probe,
115*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
116*4882a593Smuzhiyun };
117