1*4882a593SmuzhiyunRockchip RK3288 LVDS interface 2*4882a593Smuzhiyun================================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: matching the soc type, one of 6*4882a593Smuzhiyun - "rockchip,rk3288-lvds"; 7*4882a593Smuzhiyun - "rockchip,px30-lvds"; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- reg: physical base address of the controller and length 10*4882a593Smuzhiyun of memory mapped region. 11*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 12*4882a593Smuzhiyun clock-names property. 13*4882a593Smuzhiyun- clock-names: must contain "pclk_lvds" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- avdd1v0-supply: regulator phandle for 1.0V analog power 16*4882a593Smuzhiyun- avdd1v8-supply: regulator phandle for 1.8V analog power 17*4882a593Smuzhiyun- avdd3v3-supply: regulator phandle for 3.3V analog power 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- rockchip,grf: phandle to the general register files syscon 20*4882a593Smuzhiyun- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- phys: LVDS/DSI DPHY (px30 only) 23*4882a593Smuzhiyun- phy-names: name of the PHY, must be "dphy" (px30 only) 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunOptional properties: 26*4882a593Smuzhiyun- pinctrl-names: must contain a "lcdc" entry. 27*4882a593Smuzhiyun- pinctrl-0: pin control group to be used for this controller. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunRequired nodes: 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunThe lvds has two video ports as described by 32*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt 33*4882a593SmuzhiyunTheir connections are modeled using the OF graph bindings specified in 34*4882a593Smuzhiyun Documentation/devicetree/bindings/graph.txt. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl 37*4882a593Smuzhiyun- video port 1 for either a panel or subsequent encoder 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunExample: 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunlvds_panel: lvds-panel { 42*4882a593Smuzhiyun compatible = "auo,b101ean01"; 43*4882a593Smuzhiyun enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>; 44*4882a593Smuzhiyun data-mapping = "jeida-24"; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun ports { 47*4882a593Smuzhiyun panel_in_lvds: endpoint { 48*4882a593Smuzhiyun remote-endpoint = <&lvds_out_panel>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunFor Rockchip RK3288: 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun lvds: lvds@ff96c000 { 56*4882a593Smuzhiyun compatible = "rockchip,rk3288-lvds"; 57*4882a593Smuzhiyun rockchip,grf = <&grf>; 58*4882a593Smuzhiyun reg = <0xff96c000 0x4000>; 59*4882a593Smuzhiyun clocks = <&cru PCLK_LVDS_PHY>; 60*4882a593Smuzhiyun clock-names = "pclk_lvds"; 61*4882a593Smuzhiyun pinctrl-names = "lcdc"; 62*4882a593Smuzhiyun pinctrl-0 = <&lcdc_ctl>; 63*4882a593Smuzhiyun avdd1v0-supply = <&vdd10_lcd>; 64*4882a593Smuzhiyun avdd1v8-supply = <&vcc18_lcd>; 65*4882a593Smuzhiyun avdd3v3-supply = <&vcca_33>; 66*4882a593Smuzhiyun rockchip,output = "rgb"; 67*4882a593Smuzhiyun ports { 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <0>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun lvds_in: port@0 { 72*4882a593Smuzhiyun reg = <0>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun lvds_in_vopb: endpoint@0 { 75*4882a593Smuzhiyun reg = <0>; 76*4882a593Smuzhiyun remote-endpoint = <&vopb_out_lvds>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun lvds_in_vopl: endpoint@1 { 79*4882a593Smuzhiyun reg = <1>; 80*4882a593Smuzhiyun remote-endpoint = <&vopl_out_lvds>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun lvds_out: port@1 { 85*4882a593Smuzhiyun reg = <1>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun lvds_out_panel: endpoint { 88*4882a593Smuzhiyun remote-endpoint = <&panel_in_lvds>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93