boot/dts/rk3288-linux.dtsi

4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT).
6 #include <dt-bindings/soc/rockchip-system-status.h>
7 #include "rk3288-dram-default-timing.dtsi"
11 …250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 …
14 	/delete-node/ dmc@ff610000;
17 		compatible = "rockchip,rk3288-dfi";
24 		compatible = "rockchip,rk3288-dmc";
25 		devfreq-events = <&dfi>;
29 		clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0",
33 		operating-points-v2 = <&dmc_opp_table>;
34 		vop-dclk-mode = <0>;
35 		min-cpu-freq = <600000>;
37 		system-status-freq = <
50 		auto-min-freq = <396000>;
51 		auto-freq-en = <0>;
56 		compatible = "operating-points-v2";
58 		opp-192000000 {
59 			opp-hz = /bits/ 64 <192000000>;
60 			opp-microvolt = <1100000>;
62 		opp-300000000 {
63 			opp-hz = /bits/ 64 <300000000>;
64 			opp-microvolt = <1100000>;
66 		opp-396000000 {
67 			opp-hz = /bits/ 64 <396000000>;
68 			opp-microvolt = <1100000>;
70 		opp-528000000 {
71 			opp-hz = /bits/ 64 <528000000>;
72 			opp-microvolt = <1150000>;
76 	reserved-memory {
81 		drm_logo: drm-logo@00000000 {
82 			compatible = "rockchip,drm-logo";
87 	fiq-debugger {
88 		compatible = "rockchip,fiq-debugger";
90 		rockchip,serial-id = <2>;
91 		rockchip,wake-irq = <0>;
92 		rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
94 		pinctrl-names = "default";
95 		pinctrl-0 = <&uart2_xfer>;
98 	/delete-node/ timer@ff810000;
100 	display-subsystem {
104 		logo-memory-region = <&drm_logo>;
107 			route_hdmi: route-hdmi {
116 			route_edp: route-edp {
125 			route_dsi0: route-dsi0 {
134 			route_lvds: route-lvds {
143 			route_rgb: route-rgb {
156 	/* change to non-secure dmac */
161 	compatible = "rockchip,rk3288-secure-efuse";
187 	clock-names = "aclk_rga", "hclk_rga", "clk_rga";