Home
last modified time | relevance | path

Searched +full:opp +full:- +full:816000000 (Results 1 – 25 of 53) sorted by relevance

123

/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra20-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp@216000000,750 {
9 clock-latency-ns = <400000>;
10 opp-supported-hw = <0x0F 0x0003>;
11 opp-hz = /bits/ 64 <216000000>;
14 opp@216000000,800 {
15 clock-latency-ns = <400000>;
16 opp-supported-hw = <0x0F 0x0004>;
[all …]
H A Dtegra20-cpu-opp-microvolt.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 opp@216000000,750 {
6 opp-microvolt = <750000 750000 1125000>;
9 opp@216000000,800 {
10 opp-microvolt = <800000 800000 1125000>;
13 opp@312000000,750 {
14 opp-microvolt = <750000 750000 1125000>;
17 opp@312000000,800 {
18 opp-microvolt = <800000 800000 1125000>;
21 opp@456000000,750 {
[all …]
H A Drk3229.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /delete-node/ opp-table0;
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-408000000 {
18 opp-hz = /bits/ 64 <408000000>;
19 opp-microvolt = <950000>;
20 clock-latency-ns = <40000>;
21 opp-suspend;
23 opp-600000000 {
[all …]
H A Drk3229-cpu-opp.dtsi4 * This file is dual-licensed: you can use it either under the terms
44 /delete-node/ opp-table0;
47 compatible = "operating-points-v2";
48 opp-shared;
51 rockchip,max-volt = <1350000>;
52 rockchip,leakage-voltage-sel = <
56 nvmem-cells = <&cpu_leakage>;
57 nvmem-cell-names = "cpu_leakage";
59 opp-408000000 {
60 opp-hz = /bits/ 64 <408000000>;
[all …]
H A Dtegra30-cpu-opp-microvolt.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 opp@51000000,800 {
6 opp-microvolt = <800000 800000 1250000>;
9 opp@51000000,850 {
10 opp-microvolt = <850000 850000 1250000>;
13 opp@51000000,912 {
14 opp-microvolt = <912000 912000 1250000>;
17 opp@102000000,800 {
18 opp-microvolt = <800000 800000 1250000>;
21 opp@102000000,850 {
[all …]
H A Dtegra30-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp@51000000,800 {
9 clock-latency-ns = <100000>;
10 opp-supported-hw = <0x1F 0x31FE>;
11 opp-hz = /bits/ 64 <51000000>;
14 opp@51000000,850 {
15 clock-latency-ns = <100000>;
16 opp-supported-hw = <0x1F 0x0C01>;
[all …]
H A Drk3128.dtsi2 * This file is dual-licensed: you can use it either under the terms
47 compatible = "rockchip,cryptov1-rng";
50 clock-names = "clk_crypto", "hclk_crypto";
51 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
52 assigned-clock-rates = <150000000>, <100000000>;
54 reset-names = "reset";
64 compatible = "rockchip,rk3128-inno-hdmi";
68 clock-names = "aclk", "pclk";
70 pinctrl-names = "default";
71 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
[all …]
H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
H A Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
[all …]
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a5";
[all …]
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "rockchip,rk3066-smp";
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "rockchip,rk3066-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-early-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * NOTE: this file exists for the sake of early (pre-ES2) silicon. ES2 silicon
13 /delete-node/ opp-table0;
14 /delete-node/ opp-table1;
15 /delete-node/ opp-table2;
17 cluster0_opp: opp-table0 {
18 compatible = "operating-points-v2";
19 opp-shared;
21 opp-408000000 {
22 opp-hz = /bits/ 64 <408000000>;
[all …]
H A Drk3588-ipc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-linux.dtsi"
14 /delete-node/ opp-408000000;
15 /delete-node/ opp-600000000;
16 /delete-node/ opp-816000000;
17 /delete-node/ opp-1008000000;
21 /delete-node/ opp-408000000;
22 /delete-node/ opp-600000000;
23 /delete-node/ opp-816000000;
24 /delete-node/ opp-1008000000;
[all …]
H A Drk3399-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include "rk3399-sched-energy.dtsi"
9 cluster0_opp: opp-table0 {
10 compatible = "operating-points-v2";
11 opp-shared;
13 rockchip,temp-hysteresis = <5000>;
14 rockchip,low-temp = <10000>;
15 rockchip,low-temp-min-volt = <900000>;
17 nvmem-cells = <&cpul_leakage>, <&specification_serial_number>,
[all …]
H A Drk3588-nvr.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pwm/pwm.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/input/rk-input.h>
11 #include <dt-bindings/display/drm_mipi_dsi.h>
12 #include <dt-bindings/display/rockchip_vop.h>
13 #include <dt-bindings/sensor-dev.h>
14 #include "rk3588-cpu-swap.dtsi"
17 adc_keys: adc-keys {
[all …]
H A Drk3399-op1-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <800000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000>;
[all …]
H A Drk3562j-electric.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 /delete-node/ opp-408000000;
15 /delete-node/ opp-600000000;
16 /delete-node/ opp-816000000;
17 /delete-node/ opp-1008000000;
H A Drk3562j.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 compatible = "rockchip,rk3562-can";
14 clock-names = "baudclk", "apb_pclk";
16 reset-names = "can", "can-apb";
21 compatible = "rockchip,rk3562-can";
25 clock-names = "baudclk", "apb_pclk";
27 reset-names = "can", "can-apb";
33 /delete-node/ mbist-vmin;
38 /delete-node/ opp-1416000000;
39 /delete-node/ opp-1608000000;
[all …]
H A Drk3358.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /delete-node/ opp-408000000;
11 /delete-node/ opp-600000000;
12 /delete-node/ opp-816000000;
13 /delete-node/ opp-1008000000;
14 /delete-node/ opp-1200000000;
15 /delete-node/ opp-1248000000;
16 /delete-node/ opp-1296000000;
17 /delete-node/ opp-1416000000;
18 /delete-node/ opp-1512000000;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 cpu0_opp_table: opp-table-cpu {
8 compatible = "operating-points-v2";
9 opp-shared;
11 opp-648000000 {
12 opp-hz = /bits/ 64 <648000000>;
13 opp-microvolt = <1040000>;
14 clock-latency-ns = <244144>; /* 8 32k periods */
17 opp-816000000 {
18 opp-hz = /bits/ 64 <816000000>;
[all …]
H A Dsun50i-h5-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
5 cpu_opp_table: opp-table-cpu {
6 compatible = "operating-points-v2";
7 opp-shared;
9 opp-408000000 {
10 opp-hz = /bits/ 64 <408000000>;
11 opp-microvolt = <1000000 1000000 1310000>;
12 clock-latency-ns = <244144>; /* 8 32k periods */
15 opp-648000000 {
[all …]
H A Dsun50i-h6-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 cpu_opp_table: opp-table-cpu {
7 compatible = "allwinner,sun50i-h6-operating-points";
8 nvmem-cells = <&cpu_speed_grade>;
9 opp-shared;
11 opp@480000000 {
12 clock-latency-ns = <244144>; /* 8 32k periods */
13 opp-hz = /bits/ 64 <480000000>;
15 opp-microvolt-speed0 = <880000 880000 1200000>;
16 opp-microvolt-speed1 = <820000 820000 1200000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/opp/
H A Dallwinner,sun50i-h6-operating-points.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H6 CPU OPP Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 OPP varies based on the silicon variant in use. Allwinner Process
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19 provide the OPP framework with required information.
[all …]

123