1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "rk3562.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun can0: can@ff600000 { 10*4882a593Smuzhiyun compatible = "rockchip,rk3562-can"; 11*4882a593Smuzhiyun reg = <0x0 0xff600000 0x0 0x1000>; 12*4882a593Smuzhiyun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 13*4882a593Smuzhiyun clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 14*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 15*4882a593Smuzhiyun resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 16*4882a593Smuzhiyun reset-names = "can", "can-apb"; 17*4882a593Smuzhiyun status = "disabled"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun can1: can@ff610000 { 21*4882a593Smuzhiyun compatible = "rockchip,rk3562-can"; 22*4882a593Smuzhiyun reg = <0x0 0xff610000 0x0 0x1000>; 23*4882a593Smuzhiyun interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 24*4882a593Smuzhiyun clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 25*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 26*4882a593Smuzhiyun resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 27*4882a593Smuzhiyun reset-names = "can", "can-apb"; 28*4882a593Smuzhiyun status = "disabled"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&cpu0_opp_table { 33*4882a593Smuzhiyun /delete-node/ mbist-vmin; 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * Max CPU frequency is 1.8GHz for the overdrive mode, 36*4882a593Smuzhiyun * but it will reduce chip lifetime. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun /delete-node/ opp-1416000000; 39*4882a593Smuzhiyun /delete-node/ opp-1608000000; 40*4882a593Smuzhiyun /delete-node/ opp-1800000000; 41*4882a593Smuzhiyun /delete-node/ opp-2016000000; 42*4882a593Smuzhiyun opp-408000000 { 43*4882a593Smuzhiyun opp-microvolt = <850000 850000 1150000>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun opp-600000000 { 46*4882a593Smuzhiyun opp-microvolt = <850000 850000 1150000>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun opp-816000000 { 49*4882a593Smuzhiyun opp-microvolt = <850000 850000 1150000>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun opp-1008000000 { 52*4882a593Smuzhiyun opp-microvolt = <850000 850000 1150000>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun opp-1200000000 { 55*4882a593Smuzhiyun opp-microvolt-L4 = <850000 850000 1150000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun&gpu_opp_table { 60*4882a593Smuzhiyun /delete-node/ mbist-vmin; 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * Max GPU frequency is 900MHz for the overdrive mode, 63*4882a593Smuzhiyun * but it will reduce chip lifetime. 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun /delete-node/ opp-800000000; 66*4882a593Smuzhiyun /delete-node/ opp-900000000; 67*4882a593Smuzhiyun opp-300000000 { 68*4882a593Smuzhiyun opp-microvolt = <850000 850000 1000000>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun opp-400000000 { 71*4882a593Smuzhiyun opp-microvolt = <850000 850000 1000000>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun opp-500000000 { 74*4882a593Smuzhiyun opp-microvolt = <850000 850000 1000000>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun opp-600000000 { 77*4882a593Smuzhiyun opp-microvolt = <850000 850000 1000000>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun opp-700000000 { 80*4882a593Smuzhiyun opp-microvolt-L3 = <850000 850000 1000000>; 81*4882a593Smuzhiyun opp-microvolt-L4 = <850000 850000 1000000>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&npu_opp_table { 86*4882a593Smuzhiyun /delete-node/ mbist-vmin; 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * Max NPU frequency is 900MHz for the overdrive mode, 89*4882a593Smuzhiyun * but it will reduce chip lifetime. 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun /delete-node/ opp-800000000; 92*4882a593Smuzhiyun /delete-node/ opp-900000000; 93*4882a593Smuzhiyun /delete-node/ opp-1000000000; 94*4882a593Smuzhiyun opp-300000000 { 95*4882a593Smuzhiyun opp-microvolt = <850000 850000 1000000>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun opp-400000000 { 98*4882a593Smuzhiyun opp-microvolt = <850000 850000 1000000>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun opp-500000000 { 101*4882a593Smuzhiyun opp-microvolt = <850000 850000 1000000>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun opp-600000000 { 104*4882a593Smuzhiyun opp-microvolt-L2 = <850000 850000 1000000>; 105*4882a593Smuzhiyun opp-microvolt-L3 = <850000 850000 1000000>; 106*4882a593Smuzhiyun opp-microvolt-L4 = <850000 850000 1000000>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun opp-700000000 { 109*4882a593Smuzhiyun opp-microvolt-L4 = <850000 850000 1000000>; 110*4882a593Smuzhiyun status = "disabled"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun}; 113