1/* 2 * This file is dual-licensed: you can use it either under the terms 3 * of the GPL or the X11 license, at your option. Note that this dual 4 * licensing only applies to this file, and not this project as a 5 * whole. 6 * 7 * a) This file is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of the 10 * License, or (at your option) any later version. 11 * 12 * This file is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * Or, alternatively, 18 * 19 * b) Permission is hereby granted, free of charge, to any person 20 * obtaining a copy of this software and associated documentation 21 * files (the "Software"), to deal in the Software without 22 * restriction, including without limitation the rights to use, 23 * copy, modify, merge, publish, distribute, sublicense, and/or 24 * sell copies of the Software, and to permit persons to whom the 25 * Software is furnished to do so, subject to the following 26 * conditions: 27 * 28 * The above copyright notice and this permission notice shall be 29 * included in all copies or substantial portions of the Software. 30 * 31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 38 * OTHER DEALINGS IN THE SOFTWARE. 39 */ 40 41#include "rk312x.dtsi" 42 43/ { 44 compatible = "rockchip,rk3128"; 45 46 rng: rng@100fc000 { 47 compatible = "rockchip,cryptov1-rng"; 48 reg = <0x100fc000 0x4000>; 49 clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; 50 clock-names = "clk_crypto", "hclk_crypto"; 51 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>; 52 assigned-clock-rates = <150000000>, <100000000>; 53 resets = <&cru SRST_CRYPTO>; 54 reset-names = "reset"; 55 status = "disabled"; 56 }; 57 58 qos_ebc: qos@1012f080 { 59 compatible = "syscon"; 60 reg = <0x1012f080 0x20>; 61 }; 62 63 hdmi: hdmi@20034000 { 64 compatible = "rockchip,rk3128-inno-hdmi"; 65 reg = <0x20034000 0x4000>; 66 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&cru ACLK_VIO0>, <&cru PCLK_HDMI>; 68 clock-names = "aclk", "pclk"; 69 rockchip,grf = <&grf>; 70 pinctrl-names = "default"; 71 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 #sound-dai-cells = <0>; 75 status = "disabled"; 76 hdmi_in: port { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 hdmi_in_vop: endpoint@0 { 80 reg = <0>; 81 remote-endpoint = <&vop_out_hdmi>; 82 }; 83 }; 84 }; 85}; 86 87&codec { 88 /* 89 * Override the i2s_clk since codec connects to i2s_8ch in rk3128, 90 * which is different from rk3126. 91 */ 92 clock-names = "g_pclk_acodec", "i2s_clk"; 93 clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S0>; 94}; 95 96&cpu0_opp_table { 97 rockchip,leakage-scaling-sel = < 98 1 254 0 99 >; 100 rockchip,leakage-voltage-sel = < 101 1 14 0 102 15 35 1 103 36 254 2 104 >; 105 106 opp-216000000 { 107 opp-hz = /bits/ 64 <216000000>; 108 opp-microvolt = <950000 950000 1425000>; 109 opp-microvolt-L0 = <950000 950000 1425000>; 110 opp-microvolt-L1 = <950000 950000 1425000>; 111 opp-microvolt-L2 = <950000 950000 1425000>; 112 clock-latency-ns = <40000>; 113 }; 114 opp-408000000 { 115 opp-hz = /bits/ 64 <408000000>; 116 opp-microvolt = <950000 950000 1425000>; 117 opp-microvolt-L0 = <950000 950000 1425000>; 118 opp-microvolt-L1 = <950000 950000 1425000>; 119 opp-microvolt-L2 = <950000 950000 1425000>; 120 clock-latency-ns = <40000>; 121 }; 122 opp-600000000 { 123 opp-hz = /bits/ 64 <600000000>; 124 opp-microvolt-L0 = <950000 950000 1425000>; 125 opp-microvolt-L1 = <950000 950000 1425000>; 126 opp-microvolt-L2 = <950000 950000 1425000>; 127 clock-latency-ns = <40000>; 128 }; 129 opp-696000000 { 130 opp-hz = /bits/ 64 <696000000>; 131 opp-microvolt = <1150000 1150000 1425000>; 132 opp-microvolt-L0 = <975000 975000 1425000>; 133 opp-microvolt-L1 = <975000 975000 1425000>; 134 opp-microvolt-L2 = <975000 975000 1425000>; 135 clock-latency-ns = <40000>; 136 }; 137 opp-816000000 { 138 opp-hz = /bits/ 64 <816000000>; 139 opp-microvolt = <1075000 1075000 1425000>; 140 opp-microvolt-L0 = <1075000 1075000 1425000>; 141 opp-microvolt-L1 = <1050000 1050000 1425000>; 142 opp-microvolt-L2 = <1000000 1000000 1425000>; 143 clock-latency-ns = <40000>; 144 opp-suspend; 145 }; 146 opp-1008000000 { 147 opp-hz = /bits/ 64 <1008000000>; 148 opp-microvolt = <1200000 1200000 1425000>; 149 opp-microvolt-L0 = <1200000 1200000 1425000>; 150 opp-microvolt-L1 = <1175000 1175000 1425000>; 151 opp-microvolt-L2 = <1125000 1125000 1425000>; 152 clock-latency-ns = <40000>; 153 }; 154 opp-1200000000 { 155 opp-hz = /bits/ 64 <1200000000>; 156 opp-microvolt = <1325000 1325000 1425000>; 157 opp-microvolt-L0 = <1325000 1325000 1425000>; 158 opp-microvolt-L1 = <1300000 1300000 1425000>; 159 opp-microvolt-L2 = <1250000 1250000 1425000>; 160 clock-latency-ns = <40000>; 161 }; 162}; 163 164&pd_vio { 165 pm_qos = <&qos_rga>, 166 <&qos_ebc>, 167 <&qos_iep>, 168 <&qos_lcdc0>, 169 <&qos_vip0>; 170}; 171 172&sdmmc_pwren { 173 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>; 174}; 175 176&video_phy { 177 status = "okay"; 178}; 179 180&vop_mmu { 181 rockchip,skip-mmu-read; 182}; 183 184&vop_out { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 vop_out_dsi: endpoint@0 { 189 reg = <0>; 190 remote-endpoint = <&dsi_in_vop>; 191 }; 192 193 vop_out_lvds: endpoint@1 { 194 reg = <1>; 195 remote-endpoint = <&lvds_in_vop>; 196 }; 197 198 vop_out_hdmi: endpoint@2 { 199 reg = <2>; 200 remote-endpoint = <&hdmi_in_vop>; 201 }; 202}; 203