1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/* 8*4882a593Smuzhiyun * NOTE: this file exists for the sake of early (pre-ES2) silicon. ES2 silicon 9*4882a593Smuzhiyun * will have different power characteristics. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun /delete-node/ opp-table0; 14*4882a593Smuzhiyun /delete-node/ opp-table1; 15*4882a593Smuzhiyun /delete-node/ opp-table2; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cluster0_opp: opp-table0 { 18*4882a593Smuzhiyun compatible = "operating-points-v2"; 19*4882a593Smuzhiyun opp-shared; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun opp-408000000 { 22*4882a593Smuzhiyun opp-hz = /bits/ 64 <408000000>; 23*4882a593Smuzhiyun opp-microvolt = <900000 900000 1200000>; 24*4882a593Smuzhiyun clock-latency-ns = <40000>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun opp-600000000 { 27*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 28*4882a593Smuzhiyun opp-microvolt = <900000 900000 1200000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun opp-816000000 { 31*4882a593Smuzhiyun opp-hz = /bits/ 64 <816000000>; 32*4882a593Smuzhiyun opp-microvolt = <900000 900000 1200000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun opp-1008000000 { 35*4882a593Smuzhiyun opp-hz = /bits/ 64 <1008000000>; 36*4882a593Smuzhiyun opp-microvolt = <900000 900000 1200000>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun opp-1200000000 { 39*4882a593Smuzhiyun opp-hz = /bits/ 64 <1200000000>; 40*4882a593Smuzhiyun opp-microvolt = <950000 950000 1200000>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun opp-1416000000 { 43*4882a593Smuzhiyun opp-hz = /bits/ 64 <1416000000>; 44*4882a593Smuzhiyun opp-microvolt = <1050000 1050000 1200000>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun cluster1_opp: opp-table1 { 49*4882a593Smuzhiyun compatible = "operating-points-v2"; 50*4882a593Smuzhiyun opp-shared; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun opp-408000000 { 53*4882a593Smuzhiyun opp-hz = /bits/ 64 <408000000>; 54*4882a593Smuzhiyun opp-microvolt = <900000 900000 1200000>; 55*4882a593Smuzhiyun clock-latency-ns = <40000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun opp-600000000 { 58*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 59*4882a593Smuzhiyun opp-microvolt = <900000 900000 1200000>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun opp-816000000 { 62*4882a593Smuzhiyun opp-hz = /bits/ 64 <816000000>; 63*4882a593Smuzhiyun opp-microvolt = <900000 900000 1200000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun opp-1008000000 { 66*4882a593Smuzhiyun opp-hz = /bits/ 64 <1008000000>; 67*4882a593Smuzhiyun opp-microvolt = <950000 950000 1200000>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun opp-1200000000 { 70*4882a593Smuzhiyun opp-hz = /bits/ 64 <1200000000>; 71*4882a593Smuzhiyun opp-microvolt = <1000000 1000000 1200000>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun gpu_opp_table: opp-table2 { 76*4882a593Smuzhiyun compatible = "operating-points-v2"; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun opp-200000000 { 79*4882a593Smuzhiyun opp-hz = /bits/ 64 <200000000>; 80*4882a593Smuzhiyun opp-microvolt = <900000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun opp-297000000 { 83*4882a593Smuzhiyun opp-hz = /bits/ 64 <297000000>; 84*4882a593Smuzhiyun opp-microvolt = <900000>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun opp-400000000 { 87*4882a593Smuzhiyun opp-hz = /bits/ 64 <400000000>; 88*4882a593Smuzhiyun opp-microvolt = <900000>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun}; 92