1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun cluster0_opp: opp-table0 { 8*4882a593Smuzhiyun compatible = "operating-points-v2"; 9*4882a593Smuzhiyun opp-shared; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun opp00 { 12*4882a593Smuzhiyun opp-hz = /bits/ 64 <408000000>; 13*4882a593Smuzhiyun opp-microvolt = <800000>; 14*4882a593Smuzhiyun clock-latency-ns = <40000>; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun opp01 { 17*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 18*4882a593Smuzhiyun opp-microvolt = <825000>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun opp02 { 21*4882a593Smuzhiyun opp-hz = /bits/ 64 <816000000>; 22*4882a593Smuzhiyun opp-microvolt = <850000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun opp03 { 25*4882a593Smuzhiyun opp-hz = /bits/ 64 <1008000000>; 26*4882a593Smuzhiyun opp-microvolt = <900000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun opp04 { 29*4882a593Smuzhiyun opp-hz = /bits/ 64 <1200000000>; 30*4882a593Smuzhiyun opp-microvolt = <975000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun opp05 { 33*4882a593Smuzhiyun opp-hz = /bits/ 64 <1416000000>; 34*4882a593Smuzhiyun opp-microvolt = <1100000>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun opp06 { 37*4882a593Smuzhiyun opp-hz = /bits/ 64 <1512000000>; 38*4882a593Smuzhiyun opp-microvolt = <1150000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cluster1_opp: opp-table1 { 43*4882a593Smuzhiyun compatible = "operating-points-v2"; 44*4882a593Smuzhiyun opp-shared; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun opp00 { 47*4882a593Smuzhiyun opp-hz = /bits/ 64 <408000000>; 48*4882a593Smuzhiyun opp-microvolt = <800000>; 49*4882a593Smuzhiyun clock-latency-ns = <40000>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun opp01 { 52*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 53*4882a593Smuzhiyun opp-microvolt = <800000>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun opp02 { 56*4882a593Smuzhiyun opp-hz = /bits/ 64 <816000000>; 57*4882a593Smuzhiyun opp-microvolt = <825000>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun opp03 { 60*4882a593Smuzhiyun opp-hz = /bits/ 64 <1008000000>; 61*4882a593Smuzhiyun opp-microvolt = <850000>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun opp04 { 64*4882a593Smuzhiyun opp-hz = /bits/ 64 <1200000000>; 65*4882a593Smuzhiyun opp-microvolt = <900000>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun opp05 { 68*4882a593Smuzhiyun opp-hz = /bits/ 64 <1416000000>; 69*4882a593Smuzhiyun opp-microvolt = <975000>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun opp06 { 72*4882a593Smuzhiyun opp-hz = /bits/ 64 <1608000000>; 73*4882a593Smuzhiyun opp-microvolt = <1050000>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun opp07 { 76*4882a593Smuzhiyun opp-hz = /bits/ 64 <1800000000>; 77*4882a593Smuzhiyun opp-microvolt = <1150000>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun opp08 { 80*4882a593Smuzhiyun opp-hz = /bits/ 64 <2016000000>; 81*4882a593Smuzhiyun opp-microvolt = <1250000>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun gpu_opp_table: opp-table2 { 86*4882a593Smuzhiyun compatible = "operating-points-v2"; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun opp00 { 89*4882a593Smuzhiyun opp-hz = /bits/ 64 <200000000>; 90*4882a593Smuzhiyun opp-microvolt = <800000>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun opp01 { 93*4882a593Smuzhiyun opp-hz = /bits/ 64 <297000000>; 94*4882a593Smuzhiyun opp-microvolt = <800000>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun opp02 { 97*4882a593Smuzhiyun opp-hz = /bits/ 64 <400000000>; 98*4882a593Smuzhiyun opp-microvolt = <825000>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun opp03 { 101*4882a593Smuzhiyun opp-hz = /bits/ 64 <500000000>; 102*4882a593Smuzhiyun opp-microvolt = <850000>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun opp04 { 105*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 106*4882a593Smuzhiyun opp-microvolt = <925000>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun opp05 { 109*4882a593Smuzhiyun opp-hz = /bits/ 64 <800000000>; 110*4882a593Smuzhiyun opp-microvolt = <1075000>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&cpu_l0 { 116*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun&cpu_l1 { 120*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun&cpu_l2 { 124*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&cpu_l3 { 128*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&cpu_b0 { 132*4882a593Smuzhiyun operating-points-v2 = <&cluster1_opp>; 133*4882a593Smuzhiyun}; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun&cpu_b1 { 136*4882a593Smuzhiyun operating-points-v2 = <&cluster1_opp>; 137*4882a593Smuzhiyun}; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun&gpu { 140*4882a593Smuzhiyun operating-points-v2 = <&gpu_opp_table>; 141*4882a593Smuzhiyun}; 142