1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "rk322x.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun compatible = "rockchip,rk3229"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /delete-node/ opp-table0; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpu0_opp_table: opp_table0 { 14*4882a593Smuzhiyun compatible = "operating-points-v2"; 15*4882a593Smuzhiyun opp-shared; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun opp-408000000 { 18*4882a593Smuzhiyun opp-hz = /bits/ 64 <408000000>; 19*4882a593Smuzhiyun opp-microvolt = <950000>; 20*4882a593Smuzhiyun clock-latency-ns = <40000>; 21*4882a593Smuzhiyun opp-suspend; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun opp-600000000 { 24*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 25*4882a593Smuzhiyun opp-microvolt = <975000>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun opp-816000000 { 28*4882a593Smuzhiyun opp-hz = /bits/ 64 <816000000>; 29*4882a593Smuzhiyun opp-microvolt = <1000000>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun opp-1008000000 { 32*4882a593Smuzhiyun opp-hz = /bits/ 64 <1008000000>; 33*4882a593Smuzhiyun opp-microvolt = <1175000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun opp-1200000000 { 36*4882a593Smuzhiyun opp-hz = /bits/ 64 <1200000000>; 37*4882a593Smuzhiyun opp-microvolt = <1275000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun opp-1296000000 { 40*4882a593Smuzhiyun opp-hz = /bits/ 64 <1296000000>; 41*4882a593Smuzhiyun opp-microvolt = <1325000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun opp-1392000000 { 44*4882a593Smuzhiyun opp-hz = /bits/ 64 <1392000000>; 45*4882a593Smuzhiyun opp-microvolt = <1375000>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun opp-1464000000 { 48*4882a593Smuzhiyun opp-hz = /bits/ 64 <1464000000>; 49*4882a593Smuzhiyun opp-microvolt = <1400000>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53