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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "watchdog.yaml#"
13 - Jamie Iles <jamie@jamieiles.com>
17 const: snps,dw-wdt
23 description: DW Watchdog pre-timeout interrupt
29 - description: Watchdog timer reference clock
30 - description: APB3 interface clock
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
[all …]
H A Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
[all …]
H A Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
[all …]
H A Dberlin2q.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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H A Dbcm11351.dtsi2 * Copyright (C) 2012-2013 Broadcom Corporation
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
17 #include "dt-bindings/clock/bcm281xx.h"
20 #address-cells = <1>;
21 #size-cells = <1>;
24 interrupt-parent = <&gic>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a9";
[all …]
H A Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
[all …]
H A Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "rockchip,rk3066-smp";
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "rockchip,rk3066-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/synaptics/
H A Dberlin4ct.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "arm,psci-1.0", "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a53";
33 enable-method = "psci";
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A D.rk3066a-mk808.dtb.dts.tmp
H A Drk3xxx.dtsi5 * SPDX-License-Identifier: GPL-2.0+ or X11
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
39 dmac1_s: dma-controller@20018000 {
44 #dma-cells = <1>;
45 arm,pl330-broken-no-flushp;
[all …]
H A Drk3066a.dtsi5 * SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3066a-cru.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 operating-points = <
[all …]
H A D.rk3188-radxarock.dtb.dts.tmp
H A Drk3188.dtsi5 * SPDX-License-Identifier: GPL-2.0+ or X11
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3188-cru.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
26 operating-points = <
[all …]
H A Dsocfpga.dtsi4 * SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/reset/altr,rst-mgr.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
33 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
39 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
[all …]
H A Dsocfpga_arria10.dtsi2 * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
22 #address-cells = <1>;
23 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
50 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9";
[all …]
H A D.rk3368-sheep.dtb.dts.tmp
H A D.rk3368-geekbox.dtb.dts.tmp
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/realtek/
H A Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
H A Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
[all …]
/OK3568_Linux_fs/u-boot/drivers/watchdog/
H A Drockchip_wdt.c4 * SPDX-License-Identifier: GPL-2.0+
12 #include <wdt.h>
40 i = log_2_n_round_up(timeout * priv->rate / 1000) - 16; in rockchip_wdt_settimeout()
46 writel((i | (i << 4)), priv->base + WDT_TORR); in rockchip_wdt_settimeout()
53 u32 val = readl(priv->base + WDT_CR); in rockchip_wdt_enable()
60 writel(val, priv->base + WDT_CR); in rockchip_wdt_enable()
67 val = readl(priv->base + WDT_CR); in rockchip_wdt_is_enabled()
78 writel(WDT_CRR_RESTART_VAL, priv->base + WDT_CRR); in rockchip_wdt_reset()
89 if (priv->rst.dev) in rockchip_wdt_start()
90 reset_deassert(&priv->rst); in rockchip_wdt_start()
[all …]

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