xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/berlin2cd.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * based on GPL'ed 2.6 kernel sources
8*4882a593Smuzhiyun *  (c) Marvell International Ltd.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun#include <dt-bindings/clock/berlin2.h>
12*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "Marvell Armada 1500-mini (BG2CD) SoC";
16*4882a593Smuzhiyun	compatible = "marvell,berlin2cd", "marvell,berlin";
17*4882a593Smuzhiyun	#address-cells = <1>;
18*4882a593Smuzhiyun	#size-cells = <1>;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		serial0 = &uart0;
22*4882a593Smuzhiyun		serial1 = &uart1;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	cpus {
26*4882a593Smuzhiyun		#address-cells = <1>;
27*4882a593Smuzhiyun		#size-cells = <0>;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		cpu: cpu@0 {
30*4882a593Smuzhiyun			compatible = "arm,cortex-a9";
31*4882a593Smuzhiyun			device_type = "cpu";
32*4882a593Smuzhiyun			next-level-cache = <&l2>;
33*4882a593Smuzhiyun			reg = <0>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_CPU>;
36*4882a593Smuzhiyun			clock-latency = <100000>;
37*4882a593Smuzhiyun			operating-points = <
38*4882a593Smuzhiyun				/* kHz    uV */
39*4882a593Smuzhiyun				800000  1200000
40*4882a593Smuzhiyun				600000  1200000
41*4882a593Smuzhiyun			>;
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	pmu {
46*4882a593Smuzhiyun		compatible = "arm,cortex-a9-pmu";
47*4882a593Smuzhiyun		interrupt-parent = <&gic>;
48*4882a593Smuzhiyun		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	refclk: oscillator {
52*4882a593Smuzhiyun		compatible = "fixed-clock";
53*4882a593Smuzhiyun		#clock-cells = <0>;
54*4882a593Smuzhiyun		clock-frequency = <25000000>;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	soc@f7000000 {
58*4882a593Smuzhiyun		compatible = "simple-bus";
59*4882a593Smuzhiyun		#address-cells = <1>;
60*4882a593Smuzhiyun		#size-cells = <1>;
61*4882a593Smuzhiyun		interrupt-parent = <&gic>;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		ranges = <0 0xf7000000 0x1000000>;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		sdhci0: mmc@ab0000 {
66*4882a593Smuzhiyun			compatible = "mrvl,pxav3-mmc";
67*4882a593Smuzhiyun			reg = <0xab0000 0x200>;
68*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
69*4882a593Smuzhiyun			clock-names = "io", "core";
70*4882a593Smuzhiyun			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
71*4882a593Smuzhiyun			status = "disabled";
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun		l2: cache-controller@ac0000 {
75*4882a593Smuzhiyun			compatible = "arm,pl310-cache";
76*4882a593Smuzhiyun			reg = <0xac0000 0x1000>;
77*4882a593Smuzhiyun			cache-unified;
78*4882a593Smuzhiyun			cache-level = <2>;
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		snoop-control-unit@ad0000 {
82*4882a593Smuzhiyun			compatible = "arm,cortex-a9-scu";
83*4882a593Smuzhiyun			reg = <0xad0000 0x100>;
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun		gic: interrupt-controller@ad1000 {
87*4882a593Smuzhiyun			compatible = "arm,cortex-a9-gic";
88*4882a593Smuzhiyun			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
89*4882a593Smuzhiyun			interrupt-controller;
90*4882a593Smuzhiyun			#interrupt-cells = <3>;
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		global-timer@ad0200 {
94*4882a593Smuzhiyun			compatible = "arm,cortex-a9-global-timer";
95*4882a593Smuzhiyun			reg = <0xad0200 0x20>;
96*4882a593Smuzhiyun			interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
97*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_TWD>;
98*4882a593Smuzhiyun		};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun		local-timer@ad0600 {
101*4882a593Smuzhiyun			compatible = "arm,cortex-a9-twd-timer";
102*4882a593Smuzhiyun			reg = <0xad0600 0x20>;
103*4882a593Smuzhiyun			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
104*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_TWD>;
105*4882a593Smuzhiyun		};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun		local-wdt@ad0620 {
108*4882a593Smuzhiyun			compatible = "arm,cortex-a9-twd-wdt";
109*4882a593Smuzhiyun			reg = <0xad0620 0x20>;
110*4882a593Smuzhiyun			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
111*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_TWD>;
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		usb_phy0: usb-phy@b74000 {
115*4882a593Smuzhiyun			compatible = "marvell,berlin2cd-usb-phy";
116*4882a593Smuzhiyun			reg = <0xb74000 0x128>;
117*4882a593Smuzhiyun			#phy-cells = <0>;
118*4882a593Smuzhiyun			resets = <&chip_rst 0x178 23>;
119*4882a593Smuzhiyun			status = "disabled";
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		usb_phy1: usb-phy@b78000 {
123*4882a593Smuzhiyun			compatible = "marvell,berlin2cd-usb-phy";
124*4882a593Smuzhiyun			reg = <0xb78000 0x128>;
125*4882a593Smuzhiyun			#phy-cells = <0>;
126*4882a593Smuzhiyun			resets = <&chip_rst 0x178 24>;
127*4882a593Smuzhiyun			status = "disabled";
128*4882a593Smuzhiyun		};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun		eth1: ethernet@b90000 {
131*4882a593Smuzhiyun			compatible = "marvell,pxa168-eth";
132*4882a593Smuzhiyun			reg = <0xb90000 0x10000>;
133*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_GETH1>;
134*4882a593Smuzhiyun			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
135*4882a593Smuzhiyun			/* set by bootloader */
136*4882a593Smuzhiyun			local-mac-address = [00 00 00 00 00 00];
137*4882a593Smuzhiyun			#address-cells = <1>;
138*4882a593Smuzhiyun			#size-cells = <0>;
139*4882a593Smuzhiyun			phy-connection-type = "mii";
140*4882a593Smuzhiyun			phy-handle = <&ethphy1>;
141*4882a593Smuzhiyun			status = "disabled";
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun			ethphy1: ethernet-phy@0 {
144*4882a593Smuzhiyun				reg = <0>;
145*4882a593Smuzhiyun			};
146*4882a593Smuzhiyun		};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun		eth0: ethernet@e50000 {
149*4882a593Smuzhiyun			compatible = "marvell,pxa168-eth";
150*4882a593Smuzhiyun			reg = <0xe50000 0x10000>;
151*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_GETH0>;
152*4882a593Smuzhiyun			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
153*4882a593Smuzhiyun			/* set by bootloader */
154*4882a593Smuzhiyun			local-mac-address = [00 00 00 00 00 00];
155*4882a593Smuzhiyun			#address-cells = <1>;
156*4882a593Smuzhiyun			#size-cells = <0>;
157*4882a593Smuzhiyun			phy-connection-type = "mii";
158*4882a593Smuzhiyun			phy-handle = <&ethphy0>;
159*4882a593Smuzhiyun			status = "disabled";
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun			ethphy0: ethernet-phy@0 {
162*4882a593Smuzhiyun				reg = <0>;
163*4882a593Smuzhiyun			};
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun		apb@e80000 {
167*4882a593Smuzhiyun			compatible = "simple-bus";
168*4882a593Smuzhiyun			#address-cells = <1>;
169*4882a593Smuzhiyun			#size-cells = <1>;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun			ranges = <0 0xe80000 0x10000>;
172*4882a593Smuzhiyun			interrupt-parent = <&aic>;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun			gpio0: gpio@400 {
175*4882a593Smuzhiyun				compatible = "snps,dw-apb-gpio";
176*4882a593Smuzhiyun				reg = <0x0400 0x400>;
177*4882a593Smuzhiyun				#address-cells = <1>;
178*4882a593Smuzhiyun				#size-cells = <0>;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun				porta: gpio-port@0 {
181*4882a593Smuzhiyun					compatible = "snps,dw-apb-gpio-port";
182*4882a593Smuzhiyun					gpio-controller;
183*4882a593Smuzhiyun					#gpio-cells = <2>;
184*4882a593Smuzhiyun					snps,nr-gpios = <8>;
185*4882a593Smuzhiyun					reg = <0>;
186*4882a593Smuzhiyun					interrupt-controller;
187*4882a593Smuzhiyun					#interrupt-cells = <2>;
188*4882a593Smuzhiyun					interrupts = <0>;
189*4882a593Smuzhiyun				};
190*4882a593Smuzhiyun			};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun			gpio1: gpio@800 {
193*4882a593Smuzhiyun				compatible = "snps,dw-apb-gpio";
194*4882a593Smuzhiyun				reg = <0x0800 0x400>;
195*4882a593Smuzhiyun				#address-cells = <1>;
196*4882a593Smuzhiyun				#size-cells = <0>;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun				portb: gpio-port@1 {
199*4882a593Smuzhiyun					compatible = "snps,dw-apb-gpio-port";
200*4882a593Smuzhiyun					gpio-controller;
201*4882a593Smuzhiyun					#gpio-cells = <2>;
202*4882a593Smuzhiyun					snps,nr-gpios = <8>;
203*4882a593Smuzhiyun					reg = <0>;
204*4882a593Smuzhiyun					interrupt-controller;
205*4882a593Smuzhiyun					#interrupt-cells = <2>;
206*4882a593Smuzhiyun					interrupts = <1>;
207*4882a593Smuzhiyun				};
208*4882a593Smuzhiyun			};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun			gpio2: gpio@c00 {
211*4882a593Smuzhiyun				compatible = "snps,dw-apb-gpio";
212*4882a593Smuzhiyun				reg = <0x0c00 0x400>;
213*4882a593Smuzhiyun				#address-cells = <1>;
214*4882a593Smuzhiyun				#size-cells = <0>;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun				portc: gpio-port@2 {
217*4882a593Smuzhiyun					compatible = "snps,dw-apb-gpio-port";
218*4882a593Smuzhiyun					gpio-controller;
219*4882a593Smuzhiyun					#gpio-cells = <2>;
220*4882a593Smuzhiyun					snps,nr-gpios = <8>;
221*4882a593Smuzhiyun					reg = <0>;
222*4882a593Smuzhiyun					interrupt-controller;
223*4882a593Smuzhiyun					#interrupt-cells = <2>;
224*4882a593Smuzhiyun					interrupts = <2>;
225*4882a593Smuzhiyun				};
226*4882a593Smuzhiyun			};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun			gpio3: gpio@1000 {
229*4882a593Smuzhiyun				compatible = "snps,dw-apb-gpio";
230*4882a593Smuzhiyun				reg = <0x1000 0x400>;
231*4882a593Smuzhiyun				#address-cells = <1>;
232*4882a593Smuzhiyun				#size-cells = <0>;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun				portd: gpio-port@3 {
235*4882a593Smuzhiyun					compatible = "snps,dw-apb-gpio-port";
236*4882a593Smuzhiyun					gpio-controller;
237*4882a593Smuzhiyun					#gpio-cells = <2>;
238*4882a593Smuzhiyun					snps,nr-gpios = <8>;
239*4882a593Smuzhiyun					reg = <0>;
240*4882a593Smuzhiyun					interrupt-controller;
241*4882a593Smuzhiyun					#interrupt-cells = <2>;
242*4882a593Smuzhiyun					interrupts = <3>;
243*4882a593Smuzhiyun				};
244*4882a593Smuzhiyun			};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun			i2c0: i2c@1400 {
247*4882a593Smuzhiyun				compatible = "snps,designware-i2c";
248*4882a593Smuzhiyun				#address-cells = <1>;
249*4882a593Smuzhiyun				#size-cells = <0>;
250*4882a593Smuzhiyun				reg = <0x1400 0x100>;
251*4882a593Smuzhiyun				interrupts = <16>;
252*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
253*4882a593Smuzhiyun				status = "disabled";
254*4882a593Smuzhiyun			};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun			i2c1: i2c@1800 {
257*4882a593Smuzhiyun				compatible = "snps,designware-i2c";
258*4882a593Smuzhiyun				#address-cells = <1>;
259*4882a593Smuzhiyun				#size-cells = <0>;
260*4882a593Smuzhiyun				reg = <0x1800 0x100>;
261*4882a593Smuzhiyun				interrupts = <17>;
262*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
263*4882a593Smuzhiyun				status = "disabled";
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun			spi0: spi@1c00 {
267*4882a593Smuzhiyun				compatible = "snps,dw-apb-ssi";
268*4882a593Smuzhiyun				#address-cells = <1>;
269*4882a593Smuzhiyun				#size-cells = <0>;
270*4882a593Smuzhiyun				reg = <0x1c00 0x100>;
271*4882a593Smuzhiyun				interrupts = <4>;
272*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
273*4882a593Smuzhiyun				status = "disabled";
274*4882a593Smuzhiyun			};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun			wdt4: watchdog@2000 {
277*4882a593Smuzhiyun				compatible = "snps,dw-wdt";
278*4882a593Smuzhiyun				reg = <0x2000 0x100>;
279*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
280*4882a593Smuzhiyun				interrupts = <5>;
281*4882a593Smuzhiyun				status = "disabled";
282*4882a593Smuzhiyun			};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun			wdt5: watchdog@2400 {
285*4882a593Smuzhiyun				compatible = "snps,dw-wdt";
286*4882a593Smuzhiyun				reg = <0x2400 0x100>;
287*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
288*4882a593Smuzhiyun				interrupts = <6>;
289*4882a593Smuzhiyun				status = "disabled";
290*4882a593Smuzhiyun			};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun			wdt6: watchdog@2800 {
293*4882a593Smuzhiyun				compatible = "snps,dw-wdt";
294*4882a593Smuzhiyun				reg = <0x2800 0x100>;
295*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
296*4882a593Smuzhiyun				interrupts = <7>;
297*4882a593Smuzhiyun				status = "disabled";
298*4882a593Smuzhiyun			};
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun			timer0: timer@2c00 {
301*4882a593Smuzhiyun				compatible = "snps,dw-apb-timer";
302*4882a593Smuzhiyun				reg = <0x2c00 0x14>;
303*4882a593Smuzhiyun				interrupts = <8>;
304*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
305*4882a593Smuzhiyun				clock-names = "timer";
306*4882a593Smuzhiyun				status = "okay";
307*4882a593Smuzhiyun			};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun			timer1: timer@2c14 {
310*4882a593Smuzhiyun				compatible = "snps,dw-apb-timer";
311*4882a593Smuzhiyun				reg = <0x2c14 0x14>;
312*4882a593Smuzhiyun				interrupts = <9>;
313*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
314*4882a593Smuzhiyun				clock-names = "timer";
315*4882a593Smuzhiyun				status = "okay";
316*4882a593Smuzhiyun			};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun			timer2: timer@2c28 {
319*4882a593Smuzhiyun				compatible = "snps,dw-apb-timer";
320*4882a593Smuzhiyun				reg = <0x2c28 0x14>;
321*4882a593Smuzhiyun				interrupts = <10>;
322*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
323*4882a593Smuzhiyun				clock-names = "timer";
324*4882a593Smuzhiyun				status = "disabled";
325*4882a593Smuzhiyun			};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun			timer3: timer@2c3c {
328*4882a593Smuzhiyun				compatible = "snps,dw-apb-timer";
329*4882a593Smuzhiyun				reg = <0x2c3c 0x14>;
330*4882a593Smuzhiyun				interrupts = <11>;
331*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
332*4882a593Smuzhiyun				clock-names = "timer";
333*4882a593Smuzhiyun				status = "disabled";
334*4882a593Smuzhiyun			};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun			timer4: timer@2c50 {
337*4882a593Smuzhiyun				compatible = "snps,dw-apb-timer";
338*4882a593Smuzhiyun				reg = <0x2c50 0x14>;
339*4882a593Smuzhiyun				interrupts = <12>;
340*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
341*4882a593Smuzhiyun				clock-names = "timer";
342*4882a593Smuzhiyun				status = "disabled";
343*4882a593Smuzhiyun			};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun			timer5: timer@2c64 {
346*4882a593Smuzhiyun				compatible = "snps,dw-apb-timer";
347*4882a593Smuzhiyun				reg = <0x2c64 0x14>;
348*4882a593Smuzhiyun				interrupts = <13>;
349*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
350*4882a593Smuzhiyun				clock-names = "timer";
351*4882a593Smuzhiyun				status = "disabled";
352*4882a593Smuzhiyun			};
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun			timer6: timer@2c78 {
355*4882a593Smuzhiyun				compatible = "snps,dw-apb-timer";
356*4882a593Smuzhiyun				reg = <0x2c78 0x14>;
357*4882a593Smuzhiyun				interrupts = <14>;
358*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
359*4882a593Smuzhiyun				clock-names = "timer";
360*4882a593Smuzhiyun				status = "disabled";
361*4882a593Smuzhiyun			};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun			timer7: timer@2c8c {
364*4882a593Smuzhiyun				compatible = "snps,dw-apb-timer";
365*4882a593Smuzhiyun				reg = <0x2c8c 0x14>;
366*4882a593Smuzhiyun				interrupts = <15>;
367*4882a593Smuzhiyun				clocks = <&chip_clk CLKID_CFG>;
368*4882a593Smuzhiyun				clock-names = "timer";
369*4882a593Smuzhiyun				status = "disabled";
370*4882a593Smuzhiyun			};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun			aic: interrupt-controller@3000 {
373*4882a593Smuzhiyun				compatible = "snps,dw-apb-ictl";
374*4882a593Smuzhiyun				reg = <0x3000 0xc00>;
375*4882a593Smuzhiyun				interrupt-controller;
376*4882a593Smuzhiyun				#interrupt-cells = <1>;
377*4882a593Smuzhiyun				interrupt-parent = <&gic>;
378*4882a593Smuzhiyun				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
379*4882a593Smuzhiyun			};
380*4882a593Smuzhiyun		};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun		chip: chip-control@ea0000 {
383*4882a593Smuzhiyun			compatible = "simple-mfd", "syscon";
384*4882a593Smuzhiyun			reg = <0xea0000 0x400>;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun			chip_clk: clock {
387*4882a593Smuzhiyun				compatible = "marvell,berlin2-clk";
388*4882a593Smuzhiyun				#clock-cells = <1>;
389*4882a593Smuzhiyun				clocks = <&refclk>;
390*4882a593Smuzhiyun				clock-names = "refclk";
391*4882a593Smuzhiyun			};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun			soc_pinctrl: pin-controller {
394*4882a593Smuzhiyun				compatible = "marvell,berlin2cd-soc-pinctrl";
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun				uart0_pmux: uart0-pmux {
397*4882a593Smuzhiyun					groups = "G6";
398*4882a593Smuzhiyun					function = "uart0";
399*4882a593Smuzhiyun				};
400*4882a593Smuzhiyun			};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun			chip_rst: reset {
403*4882a593Smuzhiyun				compatible = "marvell,berlin2-reset";
404*4882a593Smuzhiyun				#reset-cells = <2>;
405*4882a593Smuzhiyun			};
406*4882a593Smuzhiyun		};
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun		usb0: usb@ed0000 {
409*4882a593Smuzhiyun			compatible = "chipidea,usb2";
410*4882a593Smuzhiyun			reg = <0xed0000 0x200>;
411*4882a593Smuzhiyun			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
412*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_USB0>;
413*4882a593Smuzhiyun			phys = <&usb_phy0>;
414*4882a593Smuzhiyun			phy-names = "usb-phy";
415*4882a593Smuzhiyun			status = "disabled";
416*4882a593Smuzhiyun		};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun		usb1: usb@ee0000 {
419*4882a593Smuzhiyun			compatible = "chipidea,usb2";
420*4882a593Smuzhiyun			reg = <0xee0000 0x200>;
421*4882a593Smuzhiyun			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
422*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_USB1>;
423*4882a593Smuzhiyun			phys = <&usb_phy1>;
424*4882a593Smuzhiyun			phy-names = "usb-phy";
425*4882a593Smuzhiyun			status = "disabled";
426*4882a593Smuzhiyun		};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun		pwm: pwm@f20000 {
429*4882a593Smuzhiyun			compatible = "marvell,berlin-pwm";
430*4882a593Smuzhiyun			reg = <0xf20000 0x40>;
431*4882a593Smuzhiyun			clocks = <&chip_clk CLKID_CFG>;
432*4882a593Smuzhiyun			#pwm-cells = <3>;
433*4882a593Smuzhiyun		};
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun		apb@fc0000 {
436*4882a593Smuzhiyun			compatible = "simple-bus";
437*4882a593Smuzhiyun			#address-cells = <1>;
438*4882a593Smuzhiyun			#size-cells = <1>;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun			ranges = <0 0xfc0000 0x10000>;
441*4882a593Smuzhiyun			interrupt-parent = <&sic>;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun			wdt0: watchdog@1000 {
444*4882a593Smuzhiyun				compatible = "snps,dw-wdt";
445*4882a593Smuzhiyun				reg = <0x1000 0x100>;
446*4882a593Smuzhiyun				clocks = <&refclk>;
447*4882a593Smuzhiyun				interrupts = <0>;
448*4882a593Smuzhiyun			};
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun			wdt1: watchdog@2000 {
451*4882a593Smuzhiyun				compatible = "snps,dw-wdt";
452*4882a593Smuzhiyun				reg = <0x2000 0x100>;
453*4882a593Smuzhiyun				clocks = <&refclk>;
454*4882a593Smuzhiyun				interrupts = <1>;
455*4882a593Smuzhiyun				status = "disabled";
456*4882a593Smuzhiyun			};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun			wdt2: watchdog@3000 {
459*4882a593Smuzhiyun				compatible = "snps,dw-wdt";
460*4882a593Smuzhiyun				reg = <0x3000 0x100>;
461*4882a593Smuzhiyun				clocks = <&refclk>;
462*4882a593Smuzhiyun				interrupts = <2>;
463*4882a593Smuzhiyun				status = "disabled";
464*4882a593Smuzhiyun			};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun			sm_gpio1: gpio@5000 {
467*4882a593Smuzhiyun				compatible = "snps,dw-apb-gpio";
468*4882a593Smuzhiyun				reg = <0x5000 0x400>;
469*4882a593Smuzhiyun				#address-cells = <1>;
470*4882a593Smuzhiyun				#size-cells = <0>;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun				portf: gpio-port@5 {
473*4882a593Smuzhiyun					compatible = "snps,dw-apb-gpio-port";
474*4882a593Smuzhiyun					gpio-controller;
475*4882a593Smuzhiyun					#gpio-cells = <2>;
476*4882a593Smuzhiyun					snps,nr-gpios = <8>;
477*4882a593Smuzhiyun					reg = <0>;
478*4882a593Smuzhiyun				};
479*4882a593Smuzhiyun			};
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun			spi1: spi@6000 {
482*4882a593Smuzhiyun				compatible = "snps,dw-apb-ssi";
483*4882a593Smuzhiyun				#address-cells = <1>;
484*4882a593Smuzhiyun				#size-cells = <0>;
485*4882a593Smuzhiyun				reg = <0x6000 0x100>;
486*4882a593Smuzhiyun				clocks = <&refclk>;
487*4882a593Smuzhiyun				interrupts = <5>;
488*4882a593Smuzhiyun				status = "disabled";
489*4882a593Smuzhiyun			};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun			i2c2: i2c@7000 {
492*4882a593Smuzhiyun				compatible = "snps,designware-i2c";
493*4882a593Smuzhiyun				#address-cells = <1>;
494*4882a593Smuzhiyun				#size-cells = <0>;
495*4882a593Smuzhiyun				reg = <0x7000 0x100>;
496*4882a593Smuzhiyun				interrupts = <6>;
497*4882a593Smuzhiyun				clocks = <&refclk>;
498*4882a593Smuzhiyun				status = "disabled";
499*4882a593Smuzhiyun			};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun			i2c3: i2c@8000 {
502*4882a593Smuzhiyun				compatible = "snps,designware-i2c";
503*4882a593Smuzhiyun				#address-cells = <1>;
504*4882a593Smuzhiyun				#size-cells = <0>;
505*4882a593Smuzhiyun				reg = <0x8000 0x100>;
506*4882a593Smuzhiyun				interrupts = <7>;
507*4882a593Smuzhiyun				clocks = <&refclk>;
508*4882a593Smuzhiyun				status = "disabled";
509*4882a593Smuzhiyun			};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun			sm_gpio0: gpio@c000 {
512*4882a593Smuzhiyun				compatible = "snps,dw-apb-gpio";
513*4882a593Smuzhiyun				reg = <0xc000 0x400>;
514*4882a593Smuzhiyun				#address-cells = <1>;
515*4882a593Smuzhiyun				#size-cells = <0>;
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun				porte: gpio-port@4 {
518*4882a593Smuzhiyun					compatible = "snps,dw-apb-gpio-port";
519*4882a593Smuzhiyun					gpio-controller;
520*4882a593Smuzhiyun					#gpio-cells = <2>;
521*4882a593Smuzhiyun					snps,nr-gpios = <8>;
522*4882a593Smuzhiyun					reg = <0>;
523*4882a593Smuzhiyun				};
524*4882a593Smuzhiyun			};
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun			uart0: serial@9000 {
527*4882a593Smuzhiyun				compatible = "snps,dw-apb-uart";
528*4882a593Smuzhiyun				reg = <0x9000 0x100>;
529*4882a593Smuzhiyun				reg-shift = <2>;
530*4882a593Smuzhiyun				reg-io-width = <1>;
531*4882a593Smuzhiyun				interrupts = <8>;
532*4882a593Smuzhiyun				clocks = <&refclk>;
533*4882a593Smuzhiyun				pinctrl-0 = <&uart0_pmux>;
534*4882a593Smuzhiyun				pinctrl-names = "default";
535*4882a593Smuzhiyun				status = "disabled";
536*4882a593Smuzhiyun			};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun			uart1: serial@a000 {
539*4882a593Smuzhiyun				compatible = "snps,dw-apb-uart";
540*4882a593Smuzhiyun				reg = <0xa000 0x100>;
541*4882a593Smuzhiyun				reg-shift = <2>;
542*4882a593Smuzhiyun				reg-io-width = <1>;
543*4882a593Smuzhiyun				interrupts = <9>;
544*4882a593Smuzhiyun				clocks = <&refclk>;
545*4882a593Smuzhiyun				status = "disabled";
546*4882a593Smuzhiyun			};
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun			uart2: serial@b000 {
549*4882a593Smuzhiyun				compatible = "snps,dw-apb-uart";
550*4882a593Smuzhiyun				reg = <0xb000 0x100>;
551*4882a593Smuzhiyun				reg-shift = <2>;
552*4882a593Smuzhiyun				reg-io-width = <1>;
553*4882a593Smuzhiyun				interrupts = <10>;
554*4882a593Smuzhiyun				clocks = <&refclk>;
555*4882a593Smuzhiyun				status = "disabled";
556*4882a593Smuzhiyun			};
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun			sysctrl: system-controller@d000 {
559*4882a593Smuzhiyun				compatible = "simple-mfd", "syscon";
560*4882a593Smuzhiyun				reg = <0xd000 0x100>;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun				sys_pinctrl: pin-controller {
563*4882a593Smuzhiyun					compatible = "marvell,berlin2cd-system-pinctrl";
564*4882a593Smuzhiyun				};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun				adc: adc {
567*4882a593Smuzhiyun					compatible = "marvell,berlin2-adc";
568*4882a593Smuzhiyun					interrupts = <12>, <14>;
569*4882a593Smuzhiyun					interrupt-names = "adc", "tsen";
570*4882a593Smuzhiyun				};
571*4882a593Smuzhiyun			};
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun			sic: interrupt-controller@e000 {
574*4882a593Smuzhiyun				compatible = "snps,dw-apb-ictl";
575*4882a593Smuzhiyun				reg = <0xe000 0x400>;
576*4882a593Smuzhiyun				interrupt-controller;
577*4882a593Smuzhiyun				#interrupt-cells = <1>;
578*4882a593Smuzhiyun				interrupt-parent = <&gic>;
579*4882a593Smuzhiyun				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
580*4882a593Smuzhiyun			};
581*4882a593Smuzhiyun		};
582*4882a593Smuzhiyun	};
583*4882a593Smuzhiyun};
584