1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR X11) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2018 Icenowy Zheng <icenowy@aosc.io> 4*4882a593Smuzhiyun * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <1>; 10*4882a593Smuzhiyun interrupt-parent = <&intc>; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun clocks { 13*4882a593Smuzhiyun osc24M: clk-24M { 14*4882a593Smuzhiyun #clock-cells = <0>; 15*4882a593Smuzhiyun compatible = "fixed-clock"; 16*4882a593Smuzhiyun clock-frequency = <24000000>; 17*4882a593Smuzhiyun clock-output-names = "osc24M"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun osc32k: clk-32k { 21*4882a593Smuzhiyun #clock-cells = <0>; 22*4882a593Smuzhiyun compatible = "fixed-clock"; 23*4882a593Smuzhiyun clock-frequency = <32768>; 24*4882a593Smuzhiyun clock-output-names = "osc32k"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun cpus { 29*4882a593Smuzhiyun cpu { 30*4882a593Smuzhiyun compatible = "arm,arm926ej-s"; 31*4882a593Smuzhiyun device_type = "cpu"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun soc { 36*4882a593Smuzhiyun compatible = "simple-bus"; 37*4882a593Smuzhiyun #address-cells = <1>; 38*4882a593Smuzhiyun #size-cells = <1>; 39*4882a593Smuzhiyun ranges; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun sram-controller@1c00000 { 42*4882a593Smuzhiyun compatible = "allwinner,suniv-f1c100s-system-control", 43*4882a593Smuzhiyun "allwinner,sun4i-a10-system-control"; 44*4882a593Smuzhiyun reg = <0x01c00000 0x30>; 45*4882a593Smuzhiyun #address-cells = <1>; 46*4882a593Smuzhiyun #size-cells = <1>; 47*4882a593Smuzhiyun ranges; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun sram_d: sram@10000 { 50*4882a593Smuzhiyun compatible = "mmio-sram"; 51*4882a593Smuzhiyun reg = <0x00010000 0x1000>; 52*4882a593Smuzhiyun #address-cells = <1>; 53*4882a593Smuzhiyun #size-cells = <1>; 54*4882a593Smuzhiyun ranges = <0 0x00010000 0x1000>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun otg_sram: sram-section@0 { 57*4882a593Smuzhiyun compatible = "allwinner,suniv-f1c100s-sram-d", 58*4882a593Smuzhiyun "allwinner,sun4i-a10-sram-d"; 59*4882a593Smuzhiyun reg = <0x0000 0x1000>; 60*4882a593Smuzhiyun status = "disabled"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun ccu: clock@1c20000 { 66*4882a593Smuzhiyun compatible = "allwinner,suniv-f1c100s-ccu"; 67*4882a593Smuzhiyun reg = <0x01c20000 0x400>; 68*4882a593Smuzhiyun clocks = <&osc24M>, <&osc32k>; 69*4882a593Smuzhiyun clock-names = "hosc", "losc"; 70*4882a593Smuzhiyun #clock-cells = <1>; 71*4882a593Smuzhiyun #reset-cells = <1>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun intc: interrupt-controller@1c20400 { 75*4882a593Smuzhiyun compatible = "allwinner,suniv-f1c100s-ic"; 76*4882a593Smuzhiyun reg = <0x01c20400 0x400>; 77*4882a593Smuzhiyun interrupt-controller; 78*4882a593Smuzhiyun #interrupt-cells = <1>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun pio: pinctrl@1c20800 { 82*4882a593Smuzhiyun compatible = "allwinner,suniv-f1c100s-pinctrl"; 83*4882a593Smuzhiyun reg = <0x01c20800 0x400>; 84*4882a593Smuzhiyun interrupts = <38>, <39>, <40>; 85*4882a593Smuzhiyun clocks = <&ccu 37>, <&osc24M>, <&osc32k>; 86*4882a593Smuzhiyun clock-names = "apb", "hosc", "losc"; 87*4882a593Smuzhiyun gpio-controller; 88*4882a593Smuzhiyun interrupt-controller; 89*4882a593Smuzhiyun #interrupt-cells = <3>; 90*4882a593Smuzhiyun #gpio-cells = <3>; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun uart0_pe_pins: uart0-pe-pins { 93*4882a593Smuzhiyun pins = "PE0", "PE1"; 94*4882a593Smuzhiyun function = "uart0"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun timer@1c20c00 { 99*4882a593Smuzhiyun compatible = "allwinner,suniv-f1c100s-timer"; 100*4882a593Smuzhiyun reg = <0x01c20c00 0x90>; 101*4882a593Smuzhiyun interrupts = <13>; 102*4882a593Smuzhiyun clocks = <&osc24M>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun wdt: watchdog@1c20ca0 { 106*4882a593Smuzhiyun compatible = "allwinner,suniv-f1c100s-wdt", 107*4882a593Smuzhiyun "allwinner,sun6i-a31-wdt"; 108*4882a593Smuzhiyun reg = <0x01c20ca0 0x20>; 109*4882a593Smuzhiyun interrupts = <16>; 110*4882a593Smuzhiyun clocks = <&osc32k>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun uart0: serial@1c25000 { 114*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 115*4882a593Smuzhiyun reg = <0x01c25000 0x400>; 116*4882a593Smuzhiyun interrupts = <1>; 117*4882a593Smuzhiyun reg-shift = <2>; 118*4882a593Smuzhiyun reg-io-width = <4>; 119*4882a593Smuzhiyun clocks = <&ccu 38>; 120*4882a593Smuzhiyun resets = <&ccu 24>; 121*4882a593Smuzhiyun status = "disabled"; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun uart1: serial@1c25400 { 125*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 126*4882a593Smuzhiyun reg = <0x01c25400 0x400>; 127*4882a593Smuzhiyun interrupts = <2>; 128*4882a593Smuzhiyun reg-shift = <2>; 129*4882a593Smuzhiyun reg-io-width = <4>; 130*4882a593Smuzhiyun clocks = <&ccu 39>; 131*4882a593Smuzhiyun resets = <&ccu 25>; 132*4882a593Smuzhiyun status = "disabled"; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun uart2: serial@1c25800 { 136*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 137*4882a593Smuzhiyun reg = <0x01c25800 0x400>; 138*4882a593Smuzhiyun interrupts = <3>; 139*4882a593Smuzhiyun reg-shift = <2>; 140*4882a593Smuzhiyun reg-io-width = <4>; 141*4882a593Smuzhiyun clocks = <&ccu 40>; 142*4882a593Smuzhiyun resets = <&ccu 26>; 143*4882a593Smuzhiyun status = "disabled"; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun}; 147