Searched +full:cpsw +full:- +full:mdio (Results 1 – 24 of 24) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings10 - Grygorii Strashko <grygorii.strashko@ti.com>11 - Sekhar Nori <nsekhar@ti.com>14 The 3-port switch gigabit ethernet subsystem provides ethernet packet18 the management data input output (MDIO) for physical layer device (PHY)24 - const: ti,cpsw-switch[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Grygorii Strashko <grygorii.strashko@ti.com>11 - Sekhar Nori <nsekhar@ti.com>16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),18 Input/Output (MDIO) interface for physical layer device (PHY) management,25 Peripheral Root Complex (UDMA-P) controller.47 "#address-cells": true[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/net/ti,davinci-mdio.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: TI SoC Davinci/Keystone2 MDIO Controller10 - Grygorii Strashko <grygorii.strashko@ti.com>13 TI SoC Davinci/Keystone2 MDIO Controller16 - $ref: "mdio.yaml#"21 - const: ti,davinci_mdio22 - items:[all …]
1 # SPDX-License-Identifier: GPL-2.0-only33 tristate "TI DaVinci MDIO Support"37 This driver supports TI's DaVinci MDIO module.43 bool "TI CPSW Phy mode Selection (DEPRECATED)"47 the CPSW. DEPRECATED: use PHY_TI_GMII_SEL.50 tristate "TI CPSW Switch Support"59 This driver supports TI's CPSW Ethernet Switch.62 will be called cpsw.65 tristate "TI CPSW Switch Support with switchdev"76 This driver supports TI's CPSW Ethernet Switch.[all …]
1 // SPDX-License-Identifier: GPL-2.041 #include "cpsw.h"52 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");56 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");69 struct cpsw_common *cpsw = (priv)->cpsw; \71 if (cpsw->data.dual_emac) \72 (func)((cpsw)->slaves + priv->emac_port, ##arg);\74 for (n = cpsw->data.slaves, \75 slave = cpsw->slaves; \76 n; n--) \[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * DaVinci MDIO Module driver31 * This timeout definition is a worst-case ultra defensive measure against89 * if MDIO bus is registered from DT.99 mdio_in = clk_get_rate(data->clk); in davinci_mdio_init_clk()100 div = (mdio_in / data->pdata.bus_freq) - 1; in davinci_mdio_init_clk()104 data->clk_div = div; in davinci_mdio_init_clk()106 * One mdio transaction consists of: in davinci_mdio_init_clk()115 * In the worst case, we could be kicking off a user-access immediately in davinci_mdio_init_clk()116 * after the mdio bus scan state-machine triggered its own read. If in davinci_mdio_init_clk()[all …]
1 // SPDX-License-Identifier: GPL-2.04 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/28 #include <linux/dma/ti-cppi5.h>29 #include <linux/dma/k3-udma-glue.h>33 #include "am65-cpsw-nuss.h"34 #include "k3-cppi-desc-pool.h"35 #include "am65-cpts.h"107 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */136 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); in am65_cpsw_port_set_sl_mac()137 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); in am65_cpsw_port_set_sl_mac()[all …]
1 //SPDX-License-Identifier: GPL-2.02 /* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/9 /dts-v1/;12 #include "am335x-osd335x-common.dtsi"13 #include <dt-bindings/interrupt-controller/irq.h>15 #include <dt-bindings/display/tda998x.h>18 model = "Octavo Systems OSD3358-SM-RED";19 compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";23 regulator-min-microvolt = <1800000>;24 regulator-max-microvolt = <1800000>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/11 /dts-v1/;16 model = "TI AM3359 ICE-V2";17 compatible = "ti,am3359-icev2", "ti,am33xx";25 stdout-path = &uart3;29 compatible = "regulator-fixed";30 regulator-name = "vbat";31 regulator-min-microvolt = <5000000>;32 regulator-max-microvolt = <5000000>;[all …]
7 #include <dt-bindings/bus/ti-sysc.h>8 #include <dt-bindings/clock/dm814.h>9 #include <dt-bindings/gpio/gpio.h>10 #include <dt-bindings/pinctrl/dm814x.h>14 interrupt-parent = <&intc>;15 #address-cells = <1>;16 #size-cells = <1>;34 #address-cells = <1>;35 #size-cells = <0>;37 compatible = "arm,cortex-a8";[all …]
2 compatible = "ti,am4-l4-wkup", "simple-bus";7 reg-names = "ap", "la", "ia0", "ia1";8 #address-cells = <1>;9 #size-cells = <1>;15 compatible = "simple-bus";16 #address-cells = <1>;17 #size-cells = <1>;25 compatible = "simple-bus";26 #address-cells = <1>;27 #size-cells = <1>;[all …]
2 compatible = "ti,am33xx-l4-wkup", "simple-bus";7 reg-names = "ap", "la", "ia0", "ia1";8 #address-cells = <1>;9 #size-cells = <1>;15 compatible = "simple-bus";16 #address-cells = <1>;17 #size-cells = <1>;25 compatible = "simple-bus";26 #address-cells = <1>;27 #size-cells = <1>;[all …]
2 compatible = "ti,dra7-l4-cfg", "simple-bus";6 reg-names = "ap", "la", "ia0";7 #address-cells = <1>;8 #size-cells = <1>;14 compatible = "simple-bus";15 #address-cells = <1>;16 #size-cells = <1>;47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */48 compatible = "ti,sysc-omap4", "ti,sysc";50 reg-names = "rev";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "ti,k2g-sci";11 ti,host-id = <12>;13 mbox-names = "rx", "tx";18 reg-names = "debug_messages";21 k3_pds: power-controller {22 compatible = "ti,sci-pm-domain";23 #power-domain-cells = <2>;27 compatible = "ti,k2g-sci-clk";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/9 mcu_conf: scm-conf@40f00000 {10 compatible = "syscon", "simple-mfd";12 #address-cells = <1>;13 #size-cells = <1>;17 compatible = "ti,am654-phy-gmii-sel";19 #phy-cells = <1>;24 compatible = "ti,am654-uart";26 reg-shift = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "ti,k2g-sci";11 ti,host-id = <12>;13 mbox-names = "rx", "tx";18 reg-names = "debug_messages";21 k3_pds: power-controller {22 compatible = "ti,sci-pm-domain";23 #power-domain-cells = <2>;27 compatible = "ti,k2g-sci-clk";[all …]
4 * (C) Copyright 2012-20147 * SPDX-License-Identifier: GPL-2.0+52 /* MDIO module input frequency */58 /* MDIO clock output frequency */109 #define GMACSL_RET_INVALID_PORT -1110 #define GMACSL_RET_WARN_RESET_INCOMPLETE -2111 #define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3112 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4122 /* CPSW */132 #define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1)[all …]
4 * (C) Copyright 2012-20147 * SPDX-License-Identifier: GPL-2.0+21 #include <asm/ti-common/keystone_nav.h>22 #include <asm/ti-common/keystone_net.h>23 #include <asm/ti-common/keystone_serdes.h>80 /* CPSW Switch slave registers */91 /* CPSW Switch slave registers */119 /* MDIO */124 struct mdio_regs *adap_mdio = bus->priv; in keystone2_mdio_reset()126 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; in keystone2_mdio_reset()[all …]
2 * CPSW Ethernet Switch Driver4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/23 #include <cpsw.h>34 #define BITMASK(bits) (BIT(bits) - 1)83 * This timeout definition is a worst-case ultra defensive measure against200 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */240 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)241 #define desc_read(desc, fld) __raw_readl(&(desc)->fld)242 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))244 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)[all …]
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/11 #include <dt-bindings/gpio/gpio.h>12 #include <dt-bindings/interrupt-controller/arm-gic.h>18 interrupt-parent = <&wakeupgen>;32 #address-cells = <1>;33 #size-cells = <0>;35 compatible = "arm,cortex-a9";40 clock-names = "cpu";42 clock-latency = <300000>; /* From omap-cpufreq driver */46 gic: interrupt-controller@48241000 {[all …]
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/11 #include <dt-bindings/gpio/gpio.h>12 #include <dt-bindings/pinctrl/am33xx.h>18 interrupt-parent = <&intc>;41 #address-cells = <1>;42 #size-cells = <0>;44 compatible = "arm,cortex-a8";53 operating-points = <60 voltage-tolerance = <2>; /* 2 percentage */63 clock-names = "cpu";[all …]
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/pinctrl/dra.h>16 #address-cells = <2>;17 #size-cells = <2>;20 interrupt-parent = <&crossbar_mpu>;46 compatible = "arm,armv7-timer";51 interrupt-parent = <&gic>;54 gic: interrupt-controller@48211000 {55 compatible = "arm,cortex-a15-gic";[all …]
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
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