xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/am33xx.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Device Tree Source for AM33XX SoC
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
7*4882a593Smuzhiyun * version 2.  This program is licensed "as is" without any warranty of any
8*4882a593Smuzhiyun * kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include <dt-bindings/pinctrl/am33xx.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun#include "skeleton.dtsi"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	compatible = "ti,am33xx";
18*4882a593Smuzhiyun	interrupt-parent = <&intc>;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		i2c0 = &i2c0;
22*4882a593Smuzhiyun		i2c1 = &i2c1;
23*4882a593Smuzhiyun		i2c2 = &i2c2;
24*4882a593Smuzhiyun		serial0 = &uart0;
25*4882a593Smuzhiyun		serial1 = &uart1;
26*4882a593Smuzhiyun		serial2 = &uart2;
27*4882a593Smuzhiyun		serial3 = &uart3;
28*4882a593Smuzhiyun		serial4 = &uart4;
29*4882a593Smuzhiyun		serial5 = &uart5;
30*4882a593Smuzhiyun		d_can0 = &dcan0;
31*4882a593Smuzhiyun		d_can1 = &dcan1;
32*4882a593Smuzhiyun		usb0 = &usb0;
33*4882a593Smuzhiyun		usb1 = &usb1;
34*4882a593Smuzhiyun		phy0 = &usb0_phy;
35*4882a593Smuzhiyun		phy1 = &usb1_phy;
36*4882a593Smuzhiyun		ethernet0 = &cpsw_emac0;
37*4882a593Smuzhiyun		ethernet1 = &cpsw_emac1;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	cpus {
41*4882a593Smuzhiyun		#address-cells = <1>;
42*4882a593Smuzhiyun		#size-cells = <0>;
43*4882a593Smuzhiyun		cpu@0 {
44*4882a593Smuzhiyun			compatible = "arm,cortex-a8";
45*4882a593Smuzhiyun			device_type = "cpu";
46*4882a593Smuzhiyun			reg = <0>;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun			/*
49*4882a593Smuzhiyun			 * To consider voltage drop between PMIC and SoC,
50*4882a593Smuzhiyun			 * tolerance value is reduced to 2% from 4% and
51*4882a593Smuzhiyun			 * voltage value is increased as a precaution.
52*4882a593Smuzhiyun			 */
53*4882a593Smuzhiyun			operating-points = <
54*4882a593Smuzhiyun				/* kHz    uV */
55*4882a593Smuzhiyun				720000  1285000
56*4882a593Smuzhiyun				600000  1225000
57*4882a593Smuzhiyun				500000  1125000
58*4882a593Smuzhiyun				275000  1125000
59*4882a593Smuzhiyun			>;
60*4882a593Smuzhiyun			voltage-tolerance = <2>; /* 2 percentage */
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun			clocks = <&dpll_mpu_ck>;
63*4882a593Smuzhiyun			clock-names = "cpu";
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun			clock-latency = <300000>; /* From omap-cpufreq driver */
66*4882a593Smuzhiyun		};
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	pmu {
70*4882a593Smuzhiyun		compatible = "arm,cortex-a8-pmu";
71*4882a593Smuzhiyun		interrupts = <3>;
72*4882a593Smuzhiyun	};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun	/*
75*4882a593Smuzhiyun	 * The soc node represents the soc top level view. It is used for IPs
76*4882a593Smuzhiyun	 * that are not memory mapped in the MPU view or for the MPU itself.
77*4882a593Smuzhiyun	 */
78*4882a593Smuzhiyun	soc {
79*4882a593Smuzhiyun		compatible = "ti,omap-infra";
80*4882a593Smuzhiyun		mpu {
81*4882a593Smuzhiyun			compatible = "ti,omap3-mpu";
82*4882a593Smuzhiyun			ti,hwmods = "mpu";
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	/*
87*4882a593Smuzhiyun	 * XXX: Use a flat representation of the AM33XX interconnect.
88*4882a593Smuzhiyun	 * The real AM33XX interconnect network is quite complex. Since
89*4882a593Smuzhiyun	 * it will not bring real advantage to represent that in DT
90*4882a593Smuzhiyun	 * for the moment, just use a fake OCP bus entry to represent
91*4882a593Smuzhiyun	 * the whole bus hierarchy.
92*4882a593Smuzhiyun	 */
93*4882a593Smuzhiyun	ocp {
94*4882a593Smuzhiyun		compatible = "simple-bus";
95*4882a593Smuzhiyun		#address-cells = <1>;
96*4882a593Smuzhiyun		#size-cells = <1>;
97*4882a593Smuzhiyun		ranges;
98*4882a593Smuzhiyun		ti,hwmods = "l3_main";
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun		l4_wkup: l4_wkup@44c00000 {
101*4882a593Smuzhiyun			compatible = "ti,am3-l4-wkup", "simple-bus";
102*4882a593Smuzhiyun			#address-cells = <1>;
103*4882a593Smuzhiyun			#size-cells = <1>;
104*4882a593Smuzhiyun			ranges = <0 0x44c00000 0x280000>;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun			prcm: prcm@200000 {
107*4882a593Smuzhiyun				compatible = "ti,am3-prcm";
108*4882a593Smuzhiyun				reg = <0x200000 0x4000>;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun				prcm_clocks: clocks {
111*4882a593Smuzhiyun					#address-cells = <1>;
112*4882a593Smuzhiyun					#size-cells = <0>;
113*4882a593Smuzhiyun				};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun				prcm_clockdomains: clockdomains {
116*4882a593Smuzhiyun				};
117*4882a593Smuzhiyun			};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun			scm: scm@210000 {
120*4882a593Smuzhiyun				compatible = "ti,am3-scm", "simple-bus";
121*4882a593Smuzhiyun				reg = <0x210000 0x2000>;
122*4882a593Smuzhiyun				#address-cells = <1>;
123*4882a593Smuzhiyun				#size-cells = <1>;
124*4882a593Smuzhiyun				ranges = <0 0x210000 0x2000>;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun				am33xx_pinmux: pinmux@800 {
127*4882a593Smuzhiyun					compatible = "pinctrl-single";
128*4882a593Smuzhiyun					reg = <0x800 0x238>;
129*4882a593Smuzhiyun					#address-cells = <1>;
130*4882a593Smuzhiyun					#size-cells = <0>;
131*4882a593Smuzhiyun					pinctrl-single,register-width = <32>;
132*4882a593Smuzhiyun					pinctrl-single,function-mask = <0x7f>;
133*4882a593Smuzhiyun				};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun				scm_conf: scm_conf@0 {
136*4882a593Smuzhiyun					compatible = "syscon";
137*4882a593Smuzhiyun					reg = <0x0 0x800>;
138*4882a593Smuzhiyun					#address-cells = <1>;
139*4882a593Smuzhiyun					#size-cells = <1>;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun					scm_clocks: clocks {
142*4882a593Smuzhiyun						#address-cells = <1>;
143*4882a593Smuzhiyun						#size-cells = <0>;
144*4882a593Smuzhiyun					};
145*4882a593Smuzhiyun				};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun				scm_clockdomains: clockdomains {
148*4882a593Smuzhiyun				};
149*4882a593Smuzhiyun			};
150*4882a593Smuzhiyun		};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun		intc: interrupt-controller@48200000 {
153*4882a593Smuzhiyun			compatible = "ti,am33xx-intc";
154*4882a593Smuzhiyun			interrupt-controller;
155*4882a593Smuzhiyun			#interrupt-cells = <1>;
156*4882a593Smuzhiyun			reg = <0x48200000 0x1000>;
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun		edma: edma@49000000 {
160*4882a593Smuzhiyun			compatible = "ti,edma3";
161*4882a593Smuzhiyun			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
162*4882a593Smuzhiyun			reg =	<0x49000000 0x10000>,
163*4882a593Smuzhiyun				<0x44e10f90 0x40>;
164*4882a593Smuzhiyun			interrupts = <12 13 14>;
165*4882a593Smuzhiyun			#dma-cells = <1>;
166*4882a593Smuzhiyun		};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun		gpio0: gpio@44e07000 {
169*4882a593Smuzhiyun			compatible = "ti,omap4-gpio";
170*4882a593Smuzhiyun			ti,hwmods = "gpio1";
171*4882a593Smuzhiyun			gpio-controller;
172*4882a593Smuzhiyun			#gpio-cells = <2>;
173*4882a593Smuzhiyun			interrupt-controller;
174*4882a593Smuzhiyun			#interrupt-cells = <2>;
175*4882a593Smuzhiyun			reg = <0x44e07000 0x1000>;
176*4882a593Smuzhiyun			interrupts = <96>;
177*4882a593Smuzhiyun		};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun		gpio1: gpio@4804c000 {
180*4882a593Smuzhiyun			compatible = "ti,omap4-gpio";
181*4882a593Smuzhiyun			ti,hwmods = "gpio2";
182*4882a593Smuzhiyun			gpio-controller;
183*4882a593Smuzhiyun			#gpio-cells = <2>;
184*4882a593Smuzhiyun			interrupt-controller;
185*4882a593Smuzhiyun			#interrupt-cells = <2>;
186*4882a593Smuzhiyun			reg = <0x4804c000 0x1000>;
187*4882a593Smuzhiyun			interrupts = <98>;
188*4882a593Smuzhiyun		};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun		gpio2: gpio@481ac000 {
191*4882a593Smuzhiyun			compatible = "ti,omap4-gpio";
192*4882a593Smuzhiyun			ti,hwmods = "gpio3";
193*4882a593Smuzhiyun			gpio-controller;
194*4882a593Smuzhiyun			#gpio-cells = <2>;
195*4882a593Smuzhiyun			interrupt-controller;
196*4882a593Smuzhiyun			#interrupt-cells = <2>;
197*4882a593Smuzhiyun			reg = <0x481ac000 0x1000>;
198*4882a593Smuzhiyun			interrupts = <32>;
199*4882a593Smuzhiyun		};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun		gpio3: gpio@481ae000 {
202*4882a593Smuzhiyun			compatible = "ti,omap4-gpio";
203*4882a593Smuzhiyun			ti,hwmods = "gpio4";
204*4882a593Smuzhiyun			gpio-controller;
205*4882a593Smuzhiyun			#gpio-cells = <2>;
206*4882a593Smuzhiyun			interrupt-controller;
207*4882a593Smuzhiyun			#interrupt-cells = <2>;
208*4882a593Smuzhiyun			reg = <0x481ae000 0x1000>;
209*4882a593Smuzhiyun			interrupts = <62>;
210*4882a593Smuzhiyun		};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun		uart0: serial@44e09000 {
213*4882a593Smuzhiyun			compatible = "ti,omap3-uart";
214*4882a593Smuzhiyun			ti,hwmods = "uart1";
215*4882a593Smuzhiyun			clock-frequency = <48000000>;
216*4882a593Smuzhiyun			reg = <0x44e09000 0x2000>;
217*4882a593Smuzhiyun			reg-shift = <2>;
218*4882a593Smuzhiyun			interrupts = <72>;
219*4882a593Smuzhiyun			status = "disabled";
220*4882a593Smuzhiyun			dmas = <&edma 26>, <&edma 27>;
221*4882a593Smuzhiyun			dma-names = "tx", "rx";
222*4882a593Smuzhiyun		};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun		uart1: serial@48022000 {
225*4882a593Smuzhiyun			compatible = "ti,omap3-uart";
226*4882a593Smuzhiyun			ti,hwmods = "uart2";
227*4882a593Smuzhiyun			clock-frequency = <48000000>;
228*4882a593Smuzhiyun			reg = <0x48022000 0x2000>;
229*4882a593Smuzhiyun			reg-shift = <2>;
230*4882a593Smuzhiyun			interrupts = <73>;
231*4882a593Smuzhiyun			status = "disabled";
232*4882a593Smuzhiyun			dmas = <&edma 28>, <&edma 29>;
233*4882a593Smuzhiyun			dma-names = "tx", "rx";
234*4882a593Smuzhiyun		};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun		uart2: serial@48024000 {
237*4882a593Smuzhiyun			compatible = "ti,omap3-uart";
238*4882a593Smuzhiyun			ti,hwmods = "uart3";
239*4882a593Smuzhiyun			clock-frequency = <48000000>;
240*4882a593Smuzhiyun			reg = <0x48024000 0x2000>;
241*4882a593Smuzhiyun			reg-shift = <2>;
242*4882a593Smuzhiyun			interrupts = <74>;
243*4882a593Smuzhiyun			status = "disabled";
244*4882a593Smuzhiyun			dmas = <&edma 30>, <&edma 31>;
245*4882a593Smuzhiyun			dma-names = "tx", "rx";
246*4882a593Smuzhiyun		};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun		uart3: serial@481a6000 {
249*4882a593Smuzhiyun			compatible = "ti,omap3-uart";
250*4882a593Smuzhiyun			ti,hwmods = "uart4";
251*4882a593Smuzhiyun			clock-frequency = <48000000>;
252*4882a593Smuzhiyun			reg = <0x481a6000 0x2000>;
253*4882a593Smuzhiyun			reg-shift = <2>;
254*4882a593Smuzhiyun			interrupts = <44>;
255*4882a593Smuzhiyun			status = "disabled";
256*4882a593Smuzhiyun		};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun		uart4: serial@481a8000 {
259*4882a593Smuzhiyun			compatible = "ti,omap3-uart";
260*4882a593Smuzhiyun			ti,hwmods = "uart5";
261*4882a593Smuzhiyun			clock-frequency = <48000000>;
262*4882a593Smuzhiyun			reg = <0x481a8000 0x2000>;
263*4882a593Smuzhiyun			reg-shift = <2>;
264*4882a593Smuzhiyun			interrupts = <45>;
265*4882a593Smuzhiyun			status = "disabled";
266*4882a593Smuzhiyun		};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun		uart5: serial@481aa000 {
269*4882a593Smuzhiyun			compatible = "ti,omap3-uart";
270*4882a593Smuzhiyun			ti,hwmods = "uart6";
271*4882a593Smuzhiyun			clock-frequency = <48000000>;
272*4882a593Smuzhiyun			reg = <0x481aa000 0x2000>;
273*4882a593Smuzhiyun			reg-shift = <2>;
274*4882a593Smuzhiyun			interrupts = <46>;
275*4882a593Smuzhiyun			status = "disabled";
276*4882a593Smuzhiyun		};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun		i2c0: i2c@44e0b000 {
279*4882a593Smuzhiyun			compatible = "ti,omap4-i2c";
280*4882a593Smuzhiyun			#address-cells = <1>;
281*4882a593Smuzhiyun			#size-cells = <0>;
282*4882a593Smuzhiyun			ti,hwmods = "i2c1";
283*4882a593Smuzhiyun			reg = <0x44e0b000 0x1000>;
284*4882a593Smuzhiyun			interrupts = <70>;
285*4882a593Smuzhiyun			status = "disabled";
286*4882a593Smuzhiyun		};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun		i2c1: i2c@4802a000 {
289*4882a593Smuzhiyun			compatible = "ti,omap4-i2c";
290*4882a593Smuzhiyun			#address-cells = <1>;
291*4882a593Smuzhiyun			#size-cells = <0>;
292*4882a593Smuzhiyun			ti,hwmods = "i2c2";
293*4882a593Smuzhiyun			reg = <0x4802a000 0x1000>;
294*4882a593Smuzhiyun			interrupts = <71>;
295*4882a593Smuzhiyun			status = "disabled";
296*4882a593Smuzhiyun		};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun		i2c2: i2c@4819c000 {
299*4882a593Smuzhiyun			compatible = "ti,omap4-i2c";
300*4882a593Smuzhiyun			#address-cells = <1>;
301*4882a593Smuzhiyun			#size-cells = <0>;
302*4882a593Smuzhiyun			ti,hwmods = "i2c3";
303*4882a593Smuzhiyun			reg = <0x4819c000 0x1000>;
304*4882a593Smuzhiyun			interrupts = <30>;
305*4882a593Smuzhiyun			status = "disabled";
306*4882a593Smuzhiyun		};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun		mmc1: mmc@48060000 {
309*4882a593Smuzhiyun			compatible = "ti,omap4-hsmmc";
310*4882a593Smuzhiyun			ti,hwmods = "mmc1";
311*4882a593Smuzhiyun			ti,dual-volt;
312*4882a593Smuzhiyun			ti,needs-special-reset;
313*4882a593Smuzhiyun			ti,needs-special-hs-handling;
314*4882a593Smuzhiyun			dmas = <&edma 24
315*4882a593Smuzhiyun				&edma 25>;
316*4882a593Smuzhiyun			dma-names = "tx", "rx";
317*4882a593Smuzhiyun			interrupts = <64>;
318*4882a593Smuzhiyun			reg = <0x48060000 0x1000>;
319*4882a593Smuzhiyun			status = "disabled";
320*4882a593Smuzhiyun		};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun		mmc2: mmc@481d8000 {
323*4882a593Smuzhiyun			compatible = "ti,omap4-hsmmc";
324*4882a593Smuzhiyun			ti,hwmods = "mmc2";
325*4882a593Smuzhiyun			ti,needs-special-reset;
326*4882a593Smuzhiyun			dmas = <&edma 2
327*4882a593Smuzhiyun				&edma 3>;
328*4882a593Smuzhiyun			dma-names = "tx", "rx";
329*4882a593Smuzhiyun			interrupts = <28>;
330*4882a593Smuzhiyun			reg = <0x481d8000 0x1000>;
331*4882a593Smuzhiyun			status = "disabled";
332*4882a593Smuzhiyun		};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun		mmc3: mmc@47810000 {
335*4882a593Smuzhiyun			compatible = "ti,omap4-hsmmc";
336*4882a593Smuzhiyun			ti,hwmods = "mmc3";
337*4882a593Smuzhiyun			ti,needs-special-reset;
338*4882a593Smuzhiyun			interrupts = <29>;
339*4882a593Smuzhiyun			reg = <0x47810000 0x1000>;
340*4882a593Smuzhiyun			status = "disabled";
341*4882a593Smuzhiyun		};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun		hwspinlock: spinlock@480ca000 {
344*4882a593Smuzhiyun			compatible = "ti,omap4-hwspinlock";
345*4882a593Smuzhiyun			reg = <0x480ca000 0x1000>;
346*4882a593Smuzhiyun			ti,hwmods = "spinlock";
347*4882a593Smuzhiyun			#hwlock-cells = <1>;
348*4882a593Smuzhiyun		};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun		wdt2: wdt@44e35000 {
351*4882a593Smuzhiyun			compatible = "ti,omap3-wdt";
352*4882a593Smuzhiyun			ti,hwmods = "wd_timer2";
353*4882a593Smuzhiyun			reg = <0x44e35000 0x1000>;
354*4882a593Smuzhiyun			interrupts = <91>;
355*4882a593Smuzhiyun		};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun		dcan0: can@481cc000 {
358*4882a593Smuzhiyun			compatible = "ti,am3352-d_can";
359*4882a593Smuzhiyun			ti,hwmods = "d_can0";
360*4882a593Smuzhiyun			reg = <0x481cc000 0x2000>;
361*4882a593Smuzhiyun			clocks = <&dcan0_fck>;
362*4882a593Smuzhiyun			clock-names = "fck";
363*4882a593Smuzhiyun			syscon-raminit = <&scm_conf 0x644 0>;
364*4882a593Smuzhiyun			interrupts = <52>;
365*4882a593Smuzhiyun			status = "disabled";
366*4882a593Smuzhiyun		};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun		dcan1: can@481d0000 {
369*4882a593Smuzhiyun			compatible = "ti,am3352-d_can";
370*4882a593Smuzhiyun			ti,hwmods = "d_can1";
371*4882a593Smuzhiyun			reg = <0x481d0000 0x2000>;
372*4882a593Smuzhiyun			clocks = <&dcan1_fck>;
373*4882a593Smuzhiyun			clock-names = "fck";
374*4882a593Smuzhiyun			syscon-raminit = <&scm_conf 0x644 1>;
375*4882a593Smuzhiyun			interrupts = <55>;
376*4882a593Smuzhiyun			status = "disabled";
377*4882a593Smuzhiyun		};
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun		mailbox: mailbox@480C8000 {
380*4882a593Smuzhiyun			compatible = "ti,omap4-mailbox";
381*4882a593Smuzhiyun			reg = <0x480C8000 0x200>;
382*4882a593Smuzhiyun			interrupts = <77>;
383*4882a593Smuzhiyun			ti,hwmods = "mailbox";
384*4882a593Smuzhiyun			#mbox-cells = <1>;
385*4882a593Smuzhiyun			ti,mbox-num-users = <4>;
386*4882a593Smuzhiyun			ti,mbox-num-fifos = <8>;
387*4882a593Smuzhiyun			mbox_wkupm3: wkup_m3 {
388*4882a593Smuzhiyun				ti,mbox-tx = <0 0 0>;
389*4882a593Smuzhiyun				ti,mbox-rx = <0 0 3>;
390*4882a593Smuzhiyun			};
391*4882a593Smuzhiyun		};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun		timer1: timer@44e31000 {
394*4882a593Smuzhiyun			compatible = "ti,am335x-timer-1ms";
395*4882a593Smuzhiyun			reg = <0x44e31000 0x400>;
396*4882a593Smuzhiyun			interrupts = <67>;
397*4882a593Smuzhiyun			ti,hwmods = "timer1";
398*4882a593Smuzhiyun			ti,timer-alwon;
399*4882a593Smuzhiyun		};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun		timer2: timer@48040000 {
402*4882a593Smuzhiyun			compatible = "ti,am335x-timer";
403*4882a593Smuzhiyun			reg = <0x48040000 0x400>;
404*4882a593Smuzhiyun			interrupts = <68>;
405*4882a593Smuzhiyun			ti,hwmods = "timer2";
406*4882a593Smuzhiyun		};
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun		timer3: timer@48042000 {
409*4882a593Smuzhiyun			compatible = "ti,am335x-timer";
410*4882a593Smuzhiyun			reg = <0x48042000 0x400>;
411*4882a593Smuzhiyun			interrupts = <69>;
412*4882a593Smuzhiyun			ti,hwmods = "timer3";
413*4882a593Smuzhiyun		};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun		timer4: timer@48044000 {
416*4882a593Smuzhiyun			compatible = "ti,am335x-timer";
417*4882a593Smuzhiyun			reg = <0x48044000 0x400>;
418*4882a593Smuzhiyun			interrupts = <92>;
419*4882a593Smuzhiyun			ti,hwmods = "timer4";
420*4882a593Smuzhiyun			ti,timer-pwm;
421*4882a593Smuzhiyun		};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun		timer5: timer@48046000 {
424*4882a593Smuzhiyun			compatible = "ti,am335x-timer";
425*4882a593Smuzhiyun			reg = <0x48046000 0x400>;
426*4882a593Smuzhiyun			interrupts = <93>;
427*4882a593Smuzhiyun			ti,hwmods = "timer5";
428*4882a593Smuzhiyun			ti,timer-pwm;
429*4882a593Smuzhiyun		};
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun		timer6: timer@48048000 {
432*4882a593Smuzhiyun			compatible = "ti,am335x-timer";
433*4882a593Smuzhiyun			reg = <0x48048000 0x400>;
434*4882a593Smuzhiyun			interrupts = <94>;
435*4882a593Smuzhiyun			ti,hwmods = "timer6";
436*4882a593Smuzhiyun			ti,timer-pwm;
437*4882a593Smuzhiyun		};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun		timer7: timer@4804a000 {
440*4882a593Smuzhiyun			compatible = "ti,am335x-timer";
441*4882a593Smuzhiyun			reg = <0x4804a000 0x400>;
442*4882a593Smuzhiyun			interrupts = <95>;
443*4882a593Smuzhiyun			ti,hwmods = "timer7";
444*4882a593Smuzhiyun			ti,timer-pwm;
445*4882a593Smuzhiyun		};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun		rtc: rtc@44e3e000 {
448*4882a593Smuzhiyun			compatible = "ti,am3352-rtc", "ti,da830-rtc";
449*4882a593Smuzhiyun			reg = <0x44e3e000 0x1000>;
450*4882a593Smuzhiyun			interrupts = <75
451*4882a593Smuzhiyun				      76>;
452*4882a593Smuzhiyun			ti,hwmods = "rtc";
453*4882a593Smuzhiyun		};
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun		spi0: spi@48030000 {
456*4882a593Smuzhiyun			compatible = "ti,omap4-mcspi";
457*4882a593Smuzhiyun			#address-cells = <1>;
458*4882a593Smuzhiyun			#size-cells = <0>;
459*4882a593Smuzhiyun			reg = <0x48030000 0x400>;
460*4882a593Smuzhiyun			interrupts = <65>;
461*4882a593Smuzhiyun			ti,spi-num-cs = <2>;
462*4882a593Smuzhiyun			ti,hwmods = "spi0";
463*4882a593Smuzhiyun			dmas = <&edma 16
464*4882a593Smuzhiyun				&edma 17
465*4882a593Smuzhiyun				&edma 18
466*4882a593Smuzhiyun				&edma 19>;
467*4882a593Smuzhiyun			dma-names = "tx0", "rx0", "tx1", "rx1";
468*4882a593Smuzhiyun			status = "disabled";
469*4882a593Smuzhiyun		};
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun		spi1: spi@481a0000 {
472*4882a593Smuzhiyun			compatible = "ti,omap4-mcspi";
473*4882a593Smuzhiyun			#address-cells = <1>;
474*4882a593Smuzhiyun			#size-cells = <0>;
475*4882a593Smuzhiyun			reg = <0x481a0000 0x400>;
476*4882a593Smuzhiyun			interrupts = <125>;
477*4882a593Smuzhiyun			ti,spi-num-cs = <2>;
478*4882a593Smuzhiyun			ti,hwmods = "spi1";
479*4882a593Smuzhiyun			dmas = <&edma 42
480*4882a593Smuzhiyun				&edma 43
481*4882a593Smuzhiyun				&edma 44
482*4882a593Smuzhiyun				&edma 45>;
483*4882a593Smuzhiyun			dma-names = "tx0", "rx0", "tx1", "rx1";
484*4882a593Smuzhiyun			status = "disabled";
485*4882a593Smuzhiyun		};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun		usb: usb@47400000 {
488*4882a593Smuzhiyun			compatible = "ti,am33xx-usb";
489*4882a593Smuzhiyun			reg = <0x47400000 0x1000>;
490*4882a593Smuzhiyun			ranges;
491*4882a593Smuzhiyun			#address-cells = <1>;
492*4882a593Smuzhiyun			#size-cells = <1>;
493*4882a593Smuzhiyun			ti,hwmods = "usb_otg_hs";
494*4882a593Smuzhiyun			status = "disabled";
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun			usb_ctrl_mod: control@44e10620 {
497*4882a593Smuzhiyun				compatible = "ti,am335x-usb-ctrl-module";
498*4882a593Smuzhiyun				reg = <0x44e10620 0x10
499*4882a593Smuzhiyun					0x44e10648 0x4>;
500*4882a593Smuzhiyun				reg-names = "phy_ctrl", "wakeup";
501*4882a593Smuzhiyun				status = "disabled";
502*4882a593Smuzhiyun			};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun			usb0_phy: usb-phy@47401300 {
505*4882a593Smuzhiyun				compatible = "ti,am335x-usb-phy";
506*4882a593Smuzhiyun				reg = <0x47401300 0x100>;
507*4882a593Smuzhiyun				reg-names = "phy";
508*4882a593Smuzhiyun				status = "disabled";
509*4882a593Smuzhiyun				ti,ctrl_mod = <&usb_ctrl_mod>;
510*4882a593Smuzhiyun			};
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun			usb0: usb@47401000 {
513*4882a593Smuzhiyun				compatible = "ti,musb-am33xx";
514*4882a593Smuzhiyun				status = "disabled";
515*4882a593Smuzhiyun				reg = <0x47401400 0x400
516*4882a593Smuzhiyun					0x47401000 0x200>;
517*4882a593Smuzhiyun				reg-names = "mc", "control";
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun				interrupts = <18>;
520*4882a593Smuzhiyun				interrupt-names = "mc";
521*4882a593Smuzhiyun				dr_mode = "otg";
522*4882a593Smuzhiyun				mentor,multipoint = <1>;
523*4882a593Smuzhiyun				mentor,num-eps = <16>;
524*4882a593Smuzhiyun				mentor,ram-bits = <12>;
525*4882a593Smuzhiyun				mentor,power = <500>;
526*4882a593Smuzhiyun				phys = <&usb0_phy>;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
529*4882a593Smuzhiyun					&cppi41dma  2 0 &cppi41dma  3 0
530*4882a593Smuzhiyun					&cppi41dma  4 0 &cppi41dma  5 0
531*4882a593Smuzhiyun					&cppi41dma  6 0 &cppi41dma  7 0
532*4882a593Smuzhiyun					&cppi41dma  8 0 &cppi41dma  9 0
533*4882a593Smuzhiyun					&cppi41dma 10 0 &cppi41dma 11 0
534*4882a593Smuzhiyun					&cppi41dma 12 0 &cppi41dma 13 0
535*4882a593Smuzhiyun					&cppi41dma 14 0 &cppi41dma  0 1
536*4882a593Smuzhiyun					&cppi41dma  1 1 &cppi41dma  2 1
537*4882a593Smuzhiyun					&cppi41dma  3 1 &cppi41dma  4 1
538*4882a593Smuzhiyun					&cppi41dma  5 1 &cppi41dma  6 1
539*4882a593Smuzhiyun					&cppi41dma  7 1 &cppi41dma  8 1
540*4882a593Smuzhiyun					&cppi41dma  9 1 &cppi41dma 10 1
541*4882a593Smuzhiyun					&cppi41dma 11 1 &cppi41dma 12 1
542*4882a593Smuzhiyun					&cppi41dma 13 1 &cppi41dma 14 1>;
543*4882a593Smuzhiyun				dma-names =
544*4882a593Smuzhiyun					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
545*4882a593Smuzhiyun					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
546*4882a593Smuzhiyun					"rx14", "rx15",
547*4882a593Smuzhiyun					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
548*4882a593Smuzhiyun					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
549*4882a593Smuzhiyun					"tx14", "tx15";
550*4882a593Smuzhiyun			};
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun			usb1_phy: usb-phy@47401b00 {
553*4882a593Smuzhiyun				compatible = "ti,am335x-usb-phy";
554*4882a593Smuzhiyun				reg = <0x47401b00 0x100>;
555*4882a593Smuzhiyun				reg-names = "phy";
556*4882a593Smuzhiyun				status = "disabled";
557*4882a593Smuzhiyun				ti,ctrl_mod = <&usb_ctrl_mod>;
558*4882a593Smuzhiyun			};
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun			usb1: usb@47401800 {
561*4882a593Smuzhiyun				compatible = "ti,musb-am33xx";
562*4882a593Smuzhiyun				status = "disabled";
563*4882a593Smuzhiyun				reg = <0x47401c00 0x400
564*4882a593Smuzhiyun					0x47401800 0x200>;
565*4882a593Smuzhiyun				reg-names = "mc", "control";
566*4882a593Smuzhiyun				interrupts = <19>;
567*4882a593Smuzhiyun				interrupt-names = "mc";
568*4882a593Smuzhiyun				dr_mode = "otg";
569*4882a593Smuzhiyun				mentor,multipoint = <1>;
570*4882a593Smuzhiyun				mentor,num-eps = <16>;
571*4882a593Smuzhiyun				mentor,ram-bits = <12>;
572*4882a593Smuzhiyun				mentor,power = <500>;
573*4882a593Smuzhiyun				phys = <&usb1_phy>;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
576*4882a593Smuzhiyun					&cppi41dma 17 0 &cppi41dma 18 0
577*4882a593Smuzhiyun					&cppi41dma 19 0 &cppi41dma 20 0
578*4882a593Smuzhiyun					&cppi41dma 21 0 &cppi41dma 22 0
579*4882a593Smuzhiyun					&cppi41dma 23 0 &cppi41dma 24 0
580*4882a593Smuzhiyun					&cppi41dma 25 0 &cppi41dma 26 0
581*4882a593Smuzhiyun					&cppi41dma 27 0 &cppi41dma 28 0
582*4882a593Smuzhiyun					&cppi41dma 29 0 &cppi41dma 15 1
583*4882a593Smuzhiyun					&cppi41dma 16 1 &cppi41dma 17 1
584*4882a593Smuzhiyun					&cppi41dma 18 1 &cppi41dma 19 1
585*4882a593Smuzhiyun					&cppi41dma 20 1 &cppi41dma 21 1
586*4882a593Smuzhiyun					&cppi41dma 22 1 &cppi41dma 23 1
587*4882a593Smuzhiyun					&cppi41dma 24 1 &cppi41dma 25 1
588*4882a593Smuzhiyun					&cppi41dma 26 1 &cppi41dma 27 1
589*4882a593Smuzhiyun					&cppi41dma 28 1 &cppi41dma 29 1>;
590*4882a593Smuzhiyun				dma-names =
591*4882a593Smuzhiyun					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
592*4882a593Smuzhiyun					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
593*4882a593Smuzhiyun					"rx14", "rx15",
594*4882a593Smuzhiyun					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
595*4882a593Smuzhiyun					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
596*4882a593Smuzhiyun					"tx14", "tx15";
597*4882a593Smuzhiyun			};
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun			cppi41dma: dma-controller@47402000 {
600*4882a593Smuzhiyun				compatible = "ti,am3359-cppi41";
601*4882a593Smuzhiyun				reg =  <0x47400000 0x1000
602*4882a593Smuzhiyun					0x47402000 0x1000
603*4882a593Smuzhiyun					0x47403000 0x1000
604*4882a593Smuzhiyun					0x47404000 0x4000>;
605*4882a593Smuzhiyun				reg-names = "glue", "controller", "scheduler", "queuemgr";
606*4882a593Smuzhiyun				interrupts = <17>;
607*4882a593Smuzhiyun				interrupt-names = "glue";
608*4882a593Smuzhiyun				#dma-cells = <2>;
609*4882a593Smuzhiyun				#dma-channels = <30>;
610*4882a593Smuzhiyun				#dma-requests = <256>;
611*4882a593Smuzhiyun				status = "disabled";
612*4882a593Smuzhiyun			};
613*4882a593Smuzhiyun		};
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun		epwmss0: epwmss@48300000 {
616*4882a593Smuzhiyun			compatible = "ti,am33xx-pwmss";
617*4882a593Smuzhiyun			reg = <0x48300000 0x10>;
618*4882a593Smuzhiyun			ti,hwmods = "epwmss0";
619*4882a593Smuzhiyun			#address-cells = <1>;
620*4882a593Smuzhiyun			#size-cells = <1>;
621*4882a593Smuzhiyun			status = "disabled";
622*4882a593Smuzhiyun			ranges = <0x48300100 0x48300100 0x80   /* ECAP */
623*4882a593Smuzhiyun				  0x48300180 0x48300180 0x80   /* EQEP */
624*4882a593Smuzhiyun				  0x48300200 0x48300200 0x80>; /* EHRPWM */
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun			ecap0: ecap@48300100 {
627*4882a593Smuzhiyun				compatible = "ti,am33xx-ecap";
628*4882a593Smuzhiyun				#pwm-cells = <3>;
629*4882a593Smuzhiyun				reg = <0x48300100 0x80>;
630*4882a593Smuzhiyun				interrupts = <31>;
631*4882a593Smuzhiyun				interrupt-names = "ecap0";
632*4882a593Smuzhiyun				ti,hwmods = "ecap0";
633*4882a593Smuzhiyun				status = "disabled";
634*4882a593Smuzhiyun			};
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun			ehrpwm0: ehrpwm@48300200 {
637*4882a593Smuzhiyun				compatible = "ti,am33xx-ehrpwm";
638*4882a593Smuzhiyun				#pwm-cells = <3>;
639*4882a593Smuzhiyun				reg = <0x48300200 0x80>;
640*4882a593Smuzhiyun				ti,hwmods = "ehrpwm0";
641*4882a593Smuzhiyun				status = "disabled";
642*4882a593Smuzhiyun			};
643*4882a593Smuzhiyun		};
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun		epwmss1: epwmss@48302000 {
646*4882a593Smuzhiyun			compatible = "ti,am33xx-pwmss";
647*4882a593Smuzhiyun			reg = <0x48302000 0x10>;
648*4882a593Smuzhiyun			ti,hwmods = "epwmss1";
649*4882a593Smuzhiyun			#address-cells = <1>;
650*4882a593Smuzhiyun			#size-cells = <1>;
651*4882a593Smuzhiyun			status = "disabled";
652*4882a593Smuzhiyun			ranges = <0x48302100 0x48302100 0x80   /* ECAP */
653*4882a593Smuzhiyun				  0x48302180 0x48302180 0x80   /* EQEP */
654*4882a593Smuzhiyun				  0x48302200 0x48302200 0x80>; /* EHRPWM */
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun			ecap1: ecap@48302100 {
657*4882a593Smuzhiyun				compatible = "ti,am33xx-ecap";
658*4882a593Smuzhiyun				#pwm-cells = <3>;
659*4882a593Smuzhiyun				reg = <0x48302100 0x80>;
660*4882a593Smuzhiyun				interrupts = <47>;
661*4882a593Smuzhiyun				interrupt-names = "ecap1";
662*4882a593Smuzhiyun				ti,hwmods = "ecap1";
663*4882a593Smuzhiyun				status = "disabled";
664*4882a593Smuzhiyun			};
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun			ehrpwm1: ehrpwm@48302200 {
667*4882a593Smuzhiyun				compatible = "ti,am33xx-ehrpwm";
668*4882a593Smuzhiyun				#pwm-cells = <3>;
669*4882a593Smuzhiyun				reg = <0x48302200 0x80>;
670*4882a593Smuzhiyun				ti,hwmods = "ehrpwm1";
671*4882a593Smuzhiyun				status = "disabled";
672*4882a593Smuzhiyun			};
673*4882a593Smuzhiyun		};
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun		epwmss2: epwmss@48304000 {
676*4882a593Smuzhiyun			compatible = "ti,am33xx-pwmss";
677*4882a593Smuzhiyun			reg = <0x48304000 0x10>;
678*4882a593Smuzhiyun			ti,hwmods = "epwmss2";
679*4882a593Smuzhiyun			#address-cells = <1>;
680*4882a593Smuzhiyun			#size-cells = <1>;
681*4882a593Smuzhiyun			status = "disabled";
682*4882a593Smuzhiyun			ranges = <0x48304100 0x48304100 0x80   /* ECAP */
683*4882a593Smuzhiyun				  0x48304180 0x48304180 0x80   /* EQEP */
684*4882a593Smuzhiyun				  0x48304200 0x48304200 0x80>; /* EHRPWM */
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun			ecap2: ecap@48304100 {
687*4882a593Smuzhiyun				compatible = "ti,am33xx-ecap";
688*4882a593Smuzhiyun				#pwm-cells = <3>;
689*4882a593Smuzhiyun				reg = <0x48304100 0x80>;
690*4882a593Smuzhiyun				interrupts = <61>;
691*4882a593Smuzhiyun				interrupt-names = "ecap2";
692*4882a593Smuzhiyun				ti,hwmods = "ecap2";
693*4882a593Smuzhiyun				status = "disabled";
694*4882a593Smuzhiyun			};
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun			ehrpwm2: ehrpwm@48304200 {
697*4882a593Smuzhiyun				compatible = "ti,am33xx-ehrpwm";
698*4882a593Smuzhiyun				#pwm-cells = <3>;
699*4882a593Smuzhiyun				reg = <0x48304200 0x80>;
700*4882a593Smuzhiyun				ti,hwmods = "ehrpwm2";
701*4882a593Smuzhiyun				status = "disabled";
702*4882a593Smuzhiyun			};
703*4882a593Smuzhiyun		};
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun		mac: ethernet@4a100000 {
706*4882a593Smuzhiyun			compatible = "ti,cpsw";
707*4882a593Smuzhiyun			ti,hwmods = "cpgmac0";
708*4882a593Smuzhiyun			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
709*4882a593Smuzhiyun			clock-names = "fck", "cpts";
710*4882a593Smuzhiyun			cpdma_channels = <8>;
711*4882a593Smuzhiyun			ale_entries = <1024>;
712*4882a593Smuzhiyun			bd_ram_size = <0x2000>;
713*4882a593Smuzhiyun			no_bd_ram = <0>;
714*4882a593Smuzhiyun			rx_descs = <64>;
715*4882a593Smuzhiyun			mac_control = <0x20>;
716*4882a593Smuzhiyun			slaves = <2>;
717*4882a593Smuzhiyun			active_slave = <0>;
718*4882a593Smuzhiyun			cpts_clock_mult = <0x80000000>;
719*4882a593Smuzhiyun			cpts_clock_shift = <29>;
720*4882a593Smuzhiyun			reg = <0x4a100000 0x800
721*4882a593Smuzhiyun			       0x4a101200 0x100>;
722*4882a593Smuzhiyun			#address-cells = <1>;
723*4882a593Smuzhiyun			#size-cells = <1>;
724*4882a593Smuzhiyun			/*
725*4882a593Smuzhiyun			 * c0_rx_thresh_pend
726*4882a593Smuzhiyun			 * c0_rx_pend
727*4882a593Smuzhiyun			 * c0_tx_pend
728*4882a593Smuzhiyun			 * c0_misc_pend
729*4882a593Smuzhiyun			 */
730*4882a593Smuzhiyun			interrupts = <40 41 42 43>;
731*4882a593Smuzhiyun			ranges;
732*4882a593Smuzhiyun			syscon = <&scm_conf>;
733*4882a593Smuzhiyun			status = "disabled";
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun			davinci_mdio: mdio@4a101000 {
736*4882a593Smuzhiyun				compatible = "ti,davinci_mdio";
737*4882a593Smuzhiyun				#address-cells = <1>;
738*4882a593Smuzhiyun				#size-cells = <0>;
739*4882a593Smuzhiyun				ti,hwmods = "davinci_mdio";
740*4882a593Smuzhiyun				bus_freq = <1000000>;
741*4882a593Smuzhiyun				reg = <0x4a101000 0x100>;
742*4882a593Smuzhiyun				status = "disabled";
743*4882a593Smuzhiyun			};
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun			cpsw_emac0: slave@4a100200 {
746*4882a593Smuzhiyun				/* Filled in by U-Boot */
747*4882a593Smuzhiyun				mac-address = [ 00 00 00 00 00 00 ];
748*4882a593Smuzhiyun			};
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun			cpsw_emac1: slave@4a100300 {
751*4882a593Smuzhiyun				/* Filled in by U-Boot */
752*4882a593Smuzhiyun				mac-address = [ 00 00 00 00 00 00 ];
753*4882a593Smuzhiyun			};
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun			phy_sel: cpsw-phy-sel@44e10650 {
756*4882a593Smuzhiyun				compatible = "ti,am3352-cpsw-phy-sel";
757*4882a593Smuzhiyun				reg= <0x44e10650 0x4>;
758*4882a593Smuzhiyun				reg-names = "gmii-sel";
759*4882a593Smuzhiyun			};
760*4882a593Smuzhiyun		};
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun		ocmcram: ocmcram@40300000 {
763*4882a593Smuzhiyun			compatible = "mmio-sram";
764*4882a593Smuzhiyun			reg = <0x40300000 0x10000>; /* 64k */
765*4882a593Smuzhiyun		};
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun		wkup_m3: wkup_m3@44d00000 {
768*4882a593Smuzhiyun			compatible = "ti,am3353-wkup-m3";
769*4882a593Smuzhiyun			reg = <0x44d00000 0x4000	/* M3 UMEM */
770*4882a593Smuzhiyun			       0x44d80000 0x2000>;	/* M3 DMEM */
771*4882a593Smuzhiyun			ti,hwmods = "wkup_m3";
772*4882a593Smuzhiyun			ti,no-reset-on-init;
773*4882a593Smuzhiyun		};
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun		elm: elm@48080000 {
776*4882a593Smuzhiyun			compatible = "ti,am3352-elm";
777*4882a593Smuzhiyun			reg = <0x48080000 0x2000>;
778*4882a593Smuzhiyun			interrupts = <4>;
779*4882a593Smuzhiyun			ti,hwmods = "elm";
780*4882a593Smuzhiyun			status = "disabled";
781*4882a593Smuzhiyun		};
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun		lcdc: lcdc@4830e000 {
784*4882a593Smuzhiyun			compatible = "ti,am33xx-tilcdc";
785*4882a593Smuzhiyun			reg = <0x4830e000 0x1000>;
786*4882a593Smuzhiyun			interrupts = <36>;
787*4882a593Smuzhiyun			ti,hwmods = "lcdc";
788*4882a593Smuzhiyun			status = "disabled";
789*4882a593Smuzhiyun		};
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun		tscadc: tscadc@44e0d000 {
792*4882a593Smuzhiyun			compatible = "ti,am3359-tscadc";
793*4882a593Smuzhiyun			reg = <0x44e0d000 0x1000>;
794*4882a593Smuzhiyun			interrupts = <16>;
795*4882a593Smuzhiyun			ti,hwmods = "adc_tsc";
796*4882a593Smuzhiyun			status = "disabled";
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun			tsc {
799*4882a593Smuzhiyun				compatible = "ti,am3359-tsc";
800*4882a593Smuzhiyun			};
801*4882a593Smuzhiyun			am335x_adc: adc {
802*4882a593Smuzhiyun				#io-channel-cells = <1>;
803*4882a593Smuzhiyun				compatible = "ti,am3359-adc";
804*4882a593Smuzhiyun			};
805*4882a593Smuzhiyun		};
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun		gpmc: gpmc@50000000 {
808*4882a593Smuzhiyun			compatible = "ti,am3352-gpmc";
809*4882a593Smuzhiyun			ti,hwmods = "gpmc";
810*4882a593Smuzhiyun			ti,no-idle-on-init;
811*4882a593Smuzhiyun			reg = <0x50000000 0x2000>;
812*4882a593Smuzhiyun			interrupts = <100>;
813*4882a593Smuzhiyun			gpmc,num-cs = <7>;
814*4882a593Smuzhiyun			gpmc,num-waitpins = <2>;
815*4882a593Smuzhiyun			#address-cells = <2>;
816*4882a593Smuzhiyun			#size-cells = <1>;
817*4882a593Smuzhiyun			status = "disabled";
818*4882a593Smuzhiyun		};
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun		sham: sham@53100000 {
821*4882a593Smuzhiyun			compatible = "ti,omap4-sham";
822*4882a593Smuzhiyun			ti,hwmods = "sham";
823*4882a593Smuzhiyun			reg = <0x53100000 0x200>;
824*4882a593Smuzhiyun			interrupts = <109>;
825*4882a593Smuzhiyun			dmas = <&edma 36>;
826*4882a593Smuzhiyun			dma-names = "rx";
827*4882a593Smuzhiyun		};
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun		aes: aes@53500000 {
830*4882a593Smuzhiyun			compatible = "ti,omap4-aes";
831*4882a593Smuzhiyun			ti,hwmods = "aes";
832*4882a593Smuzhiyun			reg = <0x53500000 0xa0>;
833*4882a593Smuzhiyun			interrupts = <103>;
834*4882a593Smuzhiyun			dmas = <&edma 6>,
835*4882a593Smuzhiyun			       <&edma 5>;
836*4882a593Smuzhiyun			dma-names = "tx", "rx";
837*4882a593Smuzhiyun		};
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun		mcasp0: mcasp@48038000 {
840*4882a593Smuzhiyun			compatible = "ti,am33xx-mcasp-audio";
841*4882a593Smuzhiyun			ti,hwmods = "mcasp0";
842*4882a593Smuzhiyun			reg = <0x48038000 0x2000>,
843*4882a593Smuzhiyun			      <0x46000000 0x400000>;
844*4882a593Smuzhiyun			reg-names = "mpu", "dat";
845*4882a593Smuzhiyun			interrupts = <80>, <81>;
846*4882a593Smuzhiyun			interrupt-names = "tx", "rx";
847*4882a593Smuzhiyun			status = "disabled";
848*4882a593Smuzhiyun			dmas = <&edma 8>,
849*4882a593Smuzhiyun				<&edma 9>;
850*4882a593Smuzhiyun			dma-names = "tx", "rx";
851*4882a593Smuzhiyun		};
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun		mcasp1: mcasp@4803C000 {
854*4882a593Smuzhiyun			compatible = "ti,am33xx-mcasp-audio";
855*4882a593Smuzhiyun			ti,hwmods = "mcasp1";
856*4882a593Smuzhiyun			reg = <0x4803C000 0x2000>,
857*4882a593Smuzhiyun			      <0x46400000 0x400000>;
858*4882a593Smuzhiyun			reg-names = "mpu", "dat";
859*4882a593Smuzhiyun			interrupts = <82>, <83>;
860*4882a593Smuzhiyun			interrupt-names = "tx", "rx";
861*4882a593Smuzhiyun			status = "disabled";
862*4882a593Smuzhiyun			dmas = <&edma 10>,
863*4882a593Smuzhiyun				<&edma 11>;
864*4882a593Smuzhiyun			dma-names = "tx", "rx";
865*4882a593Smuzhiyun		};
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun		rng: rng@48310000 {
868*4882a593Smuzhiyun			compatible = "ti,omap4-rng";
869*4882a593Smuzhiyun			ti,hwmods = "rng";
870*4882a593Smuzhiyun			reg = <0x48310000 0x2000>;
871*4882a593Smuzhiyun			interrupts = <111>;
872*4882a593Smuzhiyun		};
873*4882a593Smuzhiyun	};
874*4882a593Smuzhiyun};
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun/include/ "am33xx-clocks.dtsi"
877