1*4882a593Smuzhiyun//SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "am33xx.dtsi" 12*4882a593Smuzhiyun#include "am335x-osd335x-common.dtsi" 13*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun#include <dt-bindings/display/tda998x.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/ { 18*4882a593Smuzhiyun model = "Octavo Systems OSD3358-SM-RED"; 19*4882a593Smuzhiyun compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; 20*4882a593Smuzhiyun}; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun&ldo3_reg { 23*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 24*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 25*4882a593Smuzhiyun regulator-always-on; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&mmc1 { 29*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&mmc2 { 33*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 34*4882a593Smuzhiyun pinctrl-names = "default"; 35*4882a593Smuzhiyun pinctrl-0 = <&emmc_pins>; 36*4882a593Smuzhiyun bus-width = <8>; 37*4882a593Smuzhiyun status = "okay"; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&am33xx_pinmux { 41*4882a593Smuzhiyun nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { 42*4882a593Smuzhiyun pinctrl-single,pins = < 43*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) 44*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) 45*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) 46*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) 47*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) 48*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) 49*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) 50*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) 51*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) 52*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) 53*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) 54*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) 55*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) 56*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) 57*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) 58*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) 59*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) 60*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 61*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 62*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 63*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 64*4882a593Smuzhiyun >; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { 68*4882a593Smuzhiyun pinctrl-single,pins = < 69*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) 70*4882a593Smuzhiyun >; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun mcasp0_pins: mcasp0-pins { 74*4882a593Smuzhiyun pinctrl-single,pins = < 75*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) 76*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ 77*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) 78*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 79*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ 80*4882a593Smuzhiyun >; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun flash_enable: flash-enable { 84*4882a593Smuzhiyun pinctrl-single,pins = < 85*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ 86*4882a593Smuzhiyun >; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun imu_interrupt: imu-interrupt { 90*4882a593Smuzhiyun pinctrl-single,pins = < 91*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ 92*4882a593Smuzhiyun >; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun ethernet_interrupt: ethernet-interrupt{ 96*4882a593Smuzhiyun pinctrl-single,pins = < 97*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ 98*4882a593Smuzhiyun >; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&lcdc { 103*4882a593Smuzhiyun status = "okay"; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* If you want to get 24 bit RGB and 16 BGR mode instead of 106*4882a593Smuzhiyun * current 16 bit RGB and 24 BGR modes, set the propety 107*4882a593Smuzhiyun * below to "crossed" and uncomment the video-ports -property 108*4882a593Smuzhiyun * in tda19988 node. 109*4882a593Smuzhiyun * AM335x errata for wiring: 110*4882a593Smuzhiyun * https://www.ti.com/lit/er/sprz360i/sprz360i.pdf 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun blue-and-red-wiring = "straight"; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun port { 116*4882a593Smuzhiyun lcdc_0: endpoint { 117*4882a593Smuzhiyun remote-endpoint = <&hdmi_0>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun}; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun&i2c0 { 123*4882a593Smuzhiyun tda19988: hdmi-encoder@70 { 124*4882a593Smuzhiyun compatible = "nxp,tda998x"; 125*4882a593Smuzhiyun reg = <0x70>; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun pinctrl-names = "default", "off"; 128*4882a593Smuzhiyun pinctrl-0 = <&nxp_hdmi_bonelt_pins>; 129*4882a593Smuzhiyun pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ 132*4882a593Smuzhiyun /* video-ports = <0x234501>; */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #sound-dai-cells = <0>; 135*4882a593Smuzhiyun audio-ports = < TDA998x_I2S 0x03>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun port { 138*4882a593Smuzhiyun hdmi_0: endpoint { 139*4882a593Smuzhiyun remote-endpoint = <&lcdc_0>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun mpu9250: imu@68 { 145*4882a593Smuzhiyun compatible = "invensense,mpu6050"; 146*4882a593Smuzhiyun reg = <0x68>; 147*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 148*4882a593Smuzhiyun interrupts = <21 IRQ_TYPE_EDGE_RISING>; 149*4882a593Smuzhiyun i2c-gate { 150*4882a593Smuzhiyun #address-cells = <1>; 151*4882a593Smuzhiyun #size-cells = <0>; 152*4882a593Smuzhiyun ax8975@c { 153*4882a593Smuzhiyun compatible = "ak,ak8975"; 154*4882a593Smuzhiyun reg = <0x0c>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun /*invensense,int_config = <0x10>; 158*4882a593Smuzhiyun invensense,level_shifter = <0>; 159*4882a593Smuzhiyun invensense,orientation = [01 00 00 00 01 00 00 00 01]; 160*4882a593Smuzhiyun invensense,sec_slave_type = <0>; 161*4882a593Smuzhiyun invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/ 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun bmp280: pressure@76 { 165*4882a593Smuzhiyun compatible = "bosch,bmp280"; 166*4882a593Smuzhiyun reg = <0x76>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&rtc { 171*4882a593Smuzhiyun system-power-controller; 172*4882a593Smuzhiyun}; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun&mcasp0 { 175*4882a593Smuzhiyun #sound-dai-cells = <0>; 176*4882a593Smuzhiyun pinctrl-names = "default"; 177*4882a593Smuzhiyun pinctrl-0 = <&mcasp0_pins>; 178*4882a593Smuzhiyun status = "okay"; 179*4882a593Smuzhiyun op-mode = <0>; /* MCASP_IIS_MODE */ 180*4882a593Smuzhiyun tdm-slots = <2>; 181*4882a593Smuzhiyun serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 182*4882a593Smuzhiyun 0 0 1 0 183*4882a593Smuzhiyun >; 184*4882a593Smuzhiyun tx-num-evt = <32>; 185*4882a593Smuzhiyun rx-num-evt = <32>; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun/ { 189*4882a593Smuzhiyun clk_mcasp0_fixed: clk-mcasp0-fixed { 190*4882a593Smuzhiyun #clock-cells = <0>; 191*4882a593Smuzhiyun compatible = "fixed-clock"; 192*4882a593Smuzhiyun clock-frequency = <24576000>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun clk_mcasp0: clk-mcasp0 { 196*4882a593Smuzhiyun #clock-cells = <0>; 197*4882a593Smuzhiyun compatible = "gpio-gate-clock"; 198*4882a593Smuzhiyun clocks = <&clk_mcasp0_fixed>; 199*4882a593Smuzhiyun enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun sound { 203*4882a593Smuzhiyun compatible = "simple-audio-card"; 204*4882a593Smuzhiyun simple-audio-card,name = "TI BeagleBone Black"; 205*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 206*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&dailink0_master>; 207*4882a593Smuzhiyun simple-audio-card,frame-master = <&dailink0_master>; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun dailink0_master: simple-audio-card,cpu { 210*4882a593Smuzhiyun sound-dai = <&mcasp0>; 211*4882a593Smuzhiyun clocks = <&clk_mcasp0>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun simple-audio-card,codec { 215*4882a593Smuzhiyun sound-dai = <&tda19988>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun chosen { 220*4882a593Smuzhiyun stdout-path = &uart0; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun leds { 224*4882a593Smuzhiyun pinctrl-names = "default"; 225*4882a593Smuzhiyun pinctrl-0 = <&user_leds_s0>; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun compatible = "gpio-leds"; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun led2 { 230*4882a593Smuzhiyun label = "beaglebone:green:usr0"; 231*4882a593Smuzhiyun gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 232*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 233*4882a593Smuzhiyun default-state = "off"; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun led3 { 237*4882a593Smuzhiyun label = "beaglebone:green:usr1"; 238*4882a593Smuzhiyun gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 239*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 240*4882a593Smuzhiyun default-state = "off"; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun led4 { 244*4882a593Smuzhiyun label = "beaglebone:green:usr2"; 245*4882a593Smuzhiyun gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 246*4882a593Smuzhiyun linux,default-trigger = "cpu0"; 247*4882a593Smuzhiyun default-state = "off"; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun led5 { 251*4882a593Smuzhiyun label = "beaglebone:green:usr3"; 252*4882a593Smuzhiyun gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 253*4882a593Smuzhiyun linux,default-trigger = "mmc1"; 254*4882a593Smuzhiyun default-state = "off"; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun vmmcsd_fixed: fixedregulator0 { 259*4882a593Smuzhiyun compatible = "regulator-fixed"; 260*4882a593Smuzhiyun regulator-name = "vmmcsd_fixed"; 261*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 262*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun}; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun&am33xx_pinmux { 267*4882a593Smuzhiyun pinctrl-names = "default"; 268*4882a593Smuzhiyun pinctrl-0 = <&clkout2_pin>; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun user_leds_s0: user-leds-s0 { 271*4882a593Smuzhiyun pinctrl-single,pins = < 272*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ 273*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ 274*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ 275*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ 276*4882a593Smuzhiyun >; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun i2c2_pins: pinmux-i2c2-pins { 280*4882a593Smuzhiyun pinctrl-single,pins = < 281*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ 282*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ 283*4882a593Smuzhiyun >; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun uart0_pins: pinmux-uart0-pins { 287*4882a593Smuzhiyun pinctrl-single,pins = < 288*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 289*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 290*4882a593Smuzhiyun >; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun clkout2_pin: pinmux-clkout2-pin { 294*4882a593Smuzhiyun pinctrl-single,pins = < 295*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ 296*4882a593Smuzhiyun >; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun cpsw_default: cpsw-default { 300*4882a593Smuzhiyun pinctrl-single,pins = < 301*4882a593Smuzhiyun /* Slave 1 */ 302*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 303*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 304*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 305*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 306*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 307*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 308*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 309*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) 310*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) 311*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) 312*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) 313*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) 314*4882a593Smuzhiyun >; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun cpsw_sleep: cpsw-sleep { 318*4882a593Smuzhiyun pinctrl-single,pins = < 319*4882a593Smuzhiyun /* Slave 1 reset value */ 320*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 321*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 322*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 323*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 324*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 325*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 326*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 327*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 328*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 329*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 330*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 331*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 332*4882a593Smuzhiyun >; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun davinci_mdio_default: davinci-mdio-default { 336*4882a593Smuzhiyun pinctrl-single,pins = < 337*4882a593Smuzhiyun /* MDIO */ 338*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 339*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 340*4882a593Smuzhiyun >; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun davinci_mdio_sleep: davinci-mdio-sleep { 344*4882a593Smuzhiyun pinctrl-single,pins = < 345*4882a593Smuzhiyun /* MDIO reset value */ 346*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 347*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 348*4882a593Smuzhiyun >; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun mmc1_pins: pinmux-mmc1-pins { 352*4882a593Smuzhiyun pinctrl-single,pins = < 353*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ 354*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 355*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 356*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 357*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 358*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 359*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 360*4882a593Smuzhiyun >; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun emmc_pins: pinmux-emmc-pins { 364*4882a593Smuzhiyun pinctrl-single,pins = < 365*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 366*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 367*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 368*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 369*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 370*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 371*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 372*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 373*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 374*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 375*4882a593Smuzhiyun >; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun}; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun&uart0 { 381*4882a593Smuzhiyun pinctrl-names = "default"; 382*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun status = "okay"; 385*4882a593Smuzhiyun}; 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun&usb0 { 388*4882a593Smuzhiyun dr_mode = "peripheral"; 389*4882a593Smuzhiyun interrupts-extended = <&intc 18 &tps 0>; 390*4882a593Smuzhiyun interrupt-names = "mc", "vbus"; 391*4882a593Smuzhiyun}; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun&usb1 { 394*4882a593Smuzhiyun dr_mode = "host"; 395*4882a593Smuzhiyun}; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun&i2c2 { 398*4882a593Smuzhiyun pinctrl-names = "default"; 399*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 400*4882a593Smuzhiyun status = "okay"; 401*4882a593Smuzhiyun clock-frequency = <100000>; 402*4882a593Smuzhiyun}; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun&cpsw_emac0 { 405*4882a593Smuzhiyun phy-handle = <ðphy0>; 406*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 407*4882a593Smuzhiyun}; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun&mac { 410*4882a593Smuzhiyun slaves = <1>; 411*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 412*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 413*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 414*4882a593Smuzhiyun status = "okay"; 415*4882a593Smuzhiyun}; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun&davinci_mdio { 418*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 419*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 420*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 421*4882a593Smuzhiyun status = "okay"; 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun ethphy0: ethernet-phy@4 { 424*4882a593Smuzhiyun reg = <4>; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun}; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun&mmc1 { 429*4882a593Smuzhiyun status = "okay"; 430*4882a593Smuzhiyun bus-width = <0x4>; 431*4882a593Smuzhiyun pinctrl-names = "default"; 432*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 433*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 434*4882a593Smuzhiyun}; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun&rtc { 437*4882a593Smuzhiyun clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 438*4882a593Smuzhiyun clock-names = "ext-clk", "int-clk"; 439*4882a593Smuzhiyun}; 440