xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/dm814x.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
3*4882a593Smuzhiyun * version 2.  This program is licensed "as is" without any warranty of any
4*4882a593Smuzhiyun * kind, whether express or implied.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/bus/ti-sysc.h>
8*4882a593Smuzhiyun#include <dt-bindings/clock/dm814.h>
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/dm814x.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	compatible = "ti,dm814";
14*4882a593Smuzhiyun	interrupt-parent = <&intc>;
15*4882a593Smuzhiyun	#address-cells = <1>;
16*4882a593Smuzhiyun	#size-cells = <1>;
17*4882a593Smuzhiyun	chosen { };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	aliases {
20*4882a593Smuzhiyun		i2c0 = &i2c1;
21*4882a593Smuzhiyun		i2c1 = &i2c2;
22*4882a593Smuzhiyun		serial0 = &uart1;
23*4882a593Smuzhiyun		serial1 = &uart2;
24*4882a593Smuzhiyun		serial2 = &uart3;
25*4882a593Smuzhiyun		ethernet0 = &cpsw_emac0;
26*4882a593Smuzhiyun		ethernet1 = &cpsw_emac1;
27*4882a593Smuzhiyun		usb0 = &usb0;
28*4882a593Smuzhiyun		usb1 = &usb1;
29*4882a593Smuzhiyun		phy0 = &usb0_phy;
30*4882a593Smuzhiyun		phy1 = &usb1_phy;
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	cpus {
34*4882a593Smuzhiyun		#address-cells = <1>;
35*4882a593Smuzhiyun		#size-cells = <0>;
36*4882a593Smuzhiyun		cpu@0 {
37*4882a593Smuzhiyun			compatible = "arm,cortex-a8";
38*4882a593Smuzhiyun			device_type = "cpu";
39*4882a593Smuzhiyun			reg = <0>;
40*4882a593Smuzhiyun		};
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	pmu {
44*4882a593Smuzhiyun		compatible = "arm,cortex-a8-pmu";
45*4882a593Smuzhiyun		interrupts = <3>;
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun	/*
49*4882a593Smuzhiyun	 * The soc node represents the soc top level view. It is used for IPs
50*4882a593Smuzhiyun	 * that are not memory mapped in the MPU view or for the MPU itself.
51*4882a593Smuzhiyun	 */
52*4882a593Smuzhiyun	soc {
53*4882a593Smuzhiyun		compatible = "ti,omap-infra";
54*4882a593Smuzhiyun		mpu {
55*4882a593Smuzhiyun			compatible = "ti,omap3-mpu";
56*4882a593Smuzhiyun			ti,hwmods = "mpu";
57*4882a593Smuzhiyun		};
58*4882a593Smuzhiyun	};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	ocp {
61*4882a593Smuzhiyun		compatible = "simple-bus";
62*4882a593Smuzhiyun		#address-cells = <1>;
63*4882a593Smuzhiyun		#size-cells = <1>;
64*4882a593Smuzhiyun		ranges;
65*4882a593Smuzhiyun		ti,hwmods = "l3_main";
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun		usb: usb@47400000 {
68*4882a593Smuzhiyun			compatible = "ti,am33xx-usb";
69*4882a593Smuzhiyun			reg = <0x47400000 0x1000>;
70*4882a593Smuzhiyun			ranges;
71*4882a593Smuzhiyun			#address-cells = <1>;
72*4882a593Smuzhiyun			#size-cells = <1>;
73*4882a593Smuzhiyun			ti,hwmods = "usb_otg_hs";
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun			usb0_phy: usb-phy@47401300 {
76*4882a593Smuzhiyun				compatible = "ti,am335x-usb-phy";
77*4882a593Smuzhiyun				reg = <0x47401300 0x100>;
78*4882a593Smuzhiyun				reg-names = "phy";
79*4882a593Smuzhiyun				ti,ctrl_mod = <&usb_ctrl_mod>;
80*4882a593Smuzhiyun				#phy-cells = <0>;
81*4882a593Smuzhiyun			};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun			usb0: usb@47401000 {
84*4882a593Smuzhiyun				compatible = "ti,musb-am33xx";
85*4882a593Smuzhiyun				reg = <0x47401400 0x400
86*4882a593Smuzhiyun				       0x47401000 0x200>;
87*4882a593Smuzhiyun				reg-names = "mc", "control";
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun				interrupts = <18>;
90*4882a593Smuzhiyun				interrupt-names = "mc";
91*4882a593Smuzhiyun				dr_mode = "otg";
92*4882a593Smuzhiyun				mentor,multipoint = <1>;
93*4882a593Smuzhiyun				mentor,num-eps = <16>;
94*4882a593Smuzhiyun				mentor,ram-bits = <12>;
95*4882a593Smuzhiyun				mentor,power = <500>;
96*4882a593Smuzhiyun				phys = <&usb0_phy>;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
99*4882a593Smuzhiyun					&cppi41dma  2 0 &cppi41dma  3 0
100*4882a593Smuzhiyun					&cppi41dma  4 0 &cppi41dma  5 0
101*4882a593Smuzhiyun					&cppi41dma  6 0 &cppi41dma  7 0
102*4882a593Smuzhiyun					&cppi41dma  8 0 &cppi41dma  9 0
103*4882a593Smuzhiyun					&cppi41dma 10 0 &cppi41dma 11 0
104*4882a593Smuzhiyun					&cppi41dma 12 0 &cppi41dma 13 0
105*4882a593Smuzhiyun					&cppi41dma 14 0 &cppi41dma  0 1
106*4882a593Smuzhiyun					&cppi41dma  1 1 &cppi41dma  2 1
107*4882a593Smuzhiyun					&cppi41dma  3 1 &cppi41dma  4 1
108*4882a593Smuzhiyun					&cppi41dma  5 1 &cppi41dma  6 1
109*4882a593Smuzhiyun					&cppi41dma  7 1 &cppi41dma  8 1
110*4882a593Smuzhiyun					&cppi41dma  9 1 &cppi41dma 10 1
111*4882a593Smuzhiyun					&cppi41dma 11 1 &cppi41dma 12 1
112*4882a593Smuzhiyun					&cppi41dma 13 1 &cppi41dma 14 1>;
113*4882a593Smuzhiyun				dma-names =
114*4882a593Smuzhiyun					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
115*4882a593Smuzhiyun					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
116*4882a593Smuzhiyun					"rx14", "rx15",
117*4882a593Smuzhiyun					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
118*4882a593Smuzhiyun					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
119*4882a593Smuzhiyun					"tx14", "tx15";
120*4882a593Smuzhiyun			};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun			usb1: usb@47401800 {
123*4882a593Smuzhiyun				compatible = "ti,musb-am33xx";
124*4882a593Smuzhiyun				reg = <0x47401c00 0x400
125*4882a593Smuzhiyun					0x47401800 0x200>;
126*4882a593Smuzhiyun				reg-names = "mc", "control";
127*4882a593Smuzhiyun				interrupts = <19>;
128*4882a593Smuzhiyun				interrupt-names = "mc";
129*4882a593Smuzhiyun				dr_mode = "otg";
130*4882a593Smuzhiyun				mentor,multipoint = <1>;
131*4882a593Smuzhiyun				mentor,num-eps = <16>;
132*4882a593Smuzhiyun				mentor,ram-bits = <12>;
133*4882a593Smuzhiyun				mentor,power = <500>;
134*4882a593Smuzhiyun				phys = <&usb1_phy>;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
137*4882a593Smuzhiyun					&cppi41dma 17 0 &cppi41dma 18 0
138*4882a593Smuzhiyun					&cppi41dma 19 0 &cppi41dma 20 0
139*4882a593Smuzhiyun					&cppi41dma 21 0 &cppi41dma 22 0
140*4882a593Smuzhiyun					&cppi41dma 23 0 &cppi41dma 24 0
141*4882a593Smuzhiyun					&cppi41dma 25 0 &cppi41dma 26 0
142*4882a593Smuzhiyun					&cppi41dma 27 0 &cppi41dma 28 0
143*4882a593Smuzhiyun					&cppi41dma 29 0 &cppi41dma 15 1
144*4882a593Smuzhiyun					&cppi41dma 16 1 &cppi41dma 17 1
145*4882a593Smuzhiyun					&cppi41dma 18 1 &cppi41dma 19 1
146*4882a593Smuzhiyun					&cppi41dma 20 1 &cppi41dma 21 1
147*4882a593Smuzhiyun					&cppi41dma 22 1 &cppi41dma 23 1
148*4882a593Smuzhiyun					&cppi41dma 24 1 &cppi41dma 25 1
149*4882a593Smuzhiyun					&cppi41dma 26 1 &cppi41dma 27 1
150*4882a593Smuzhiyun					&cppi41dma 28 1 &cppi41dma 29 1>;
151*4882a593Smuzhiyun				dma-names =
152*4882a593Smuzhiyun					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
153*4882a593Smuzhiyun					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
154*4882a593Smuzhiyun					"rx14", "rx15",
155*4882a593Smuzhiyun					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
156*4882a593Smuzhiyun					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
157*4882a593Smuzhiyun					"tx14", "tx15";
158*4882a593Smuzhiyun			};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun			cppi41dma: dma-controller@47402000 {
161*4882a593Smuzhiyun				compatible = "ti,am3359-cppi41";
162*4882a593Smuzhiyun				reg =  <0x47400000 0x1000
163*4882a593Smuzhiyun					0x47402000 0x1000
164*4882a593Smuzhiyun					0x47403000 0x1000
165*4882a593Smuzhiyun					0x47404000 0x4000>;
166*4882a593Smuzhiyun				reg-names = "glue", "controller", "scheduler", "queuemgr";
167*4882a593Smuzhiyun				interrupts = <17>;
168*4882a593Smuzhiyun				interrupt-names = "glue";
169*4882a593Smuzhiyun				#dma-cells = <2>;
170*4882a593Smuzhiyun				#dma-channels = <30>;
171*4882a593Smuzhiyun				#dma-requests = <256>;
172*4882a593Smuzhiyun			};
173*4882a593Smuzhiyun		};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun		/*
176*4882a593Smuzhiyun		 * See TRM "Table 1-317. L4LS Instance Summary" for hints.
177*4882a593Smuzhiyun		 * It shows the module target agent registers though, so the
178*4882a593Smuzhiyun		 * actual device is typically 0x1000 before the target agent
179*4882a593Smuzhiyun		 * except in cases where the module is larger than 0x1000.
180*4882a593Smuzhiyun		 */
181*4882a593Smuzhiyun		l4ls: l4ls@48000000 {
182*4882a593Smuzhiyun			compatible = "ti,dm814-l4ls", "simple-bus";
183*4882a593Smuzhiyun			#address-cells = <1>;
184*4882a593Smuzhiyun			#size-cells = <1>;
185*4882a593Smuzhiyun			ranges = <0 0x48000000 0x2000000>;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun			i2c1: i2c@28000 {
188*4882a593Smuzhiyun				compatible = "ti,omap4-i2c";
189*4882a593Smuzhiyun				#address-cells = <1>;
190*4882a593Smuzhiyun				#size-cells = <0>;
191*4882a593Smuzhiyun				ti,hwmods = "i2c1";
192*4882a593Smuzhiyun				reg = <0x28000 0x1000>;
193*4882a593Smuzhiyun				interrupts = <70>;
194*4882a593Smuzhiyun			};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun			elm: elm@80000 {
197*4882a593Smuzhiyun				compatible = "ti,814-elm";
198*4882a593Smuzhiyun				ti,hwmods = "elm";
199*4882a593Smuzhiyun				reg = <0x80000 0x2000>;
200*4882a593Smuzhiyun				interrupts = <4>;
201*4882a593Smuzhiyun			};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun			gpio1: gpio@32000 {
204*4882a593Smuzhiyun				compatible = "ti,omap4-gpio";
205*4882a593Smuzhiyun				ti,hwmods = "gpio1";
206*4882a593Smuzhiyun				ti,gpio-always-on;
207*4882a593Smuzhiyun				reg = <0x32000 0x2000>;
208*4882a593Smuzhiyun				interrupts = <96>;
209*4882a593Smuzhiyun				gpio-controller;
210*4882a593Smuzhiyun				#gpio-cells = <2>;
211*4882a593Smuzhiyun				interrupt-controller;
212*4882a593Smuzhiyun				#interrupt-cells = <2>;
213*4882a593Smuzhiyun			};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun			gpio2: gpio@4c000 {
216*4882a593Smuzhiyun				compatible = "ti,omap4-gpio";
217*4882a593Smuzhiyun				ti,hwmods = "gpio2";
218*4882a593Smuzhiyun				ti,gpio-always-on;
219*4882a593Smuzhiyun				reg = <0x4c000 0x2000>;
220*4882a593Smuzhiyun				interrupts = <98>;
221*4882a593Smuzhiyun				gpio-controller;
222*4882a593Smuzhiyun				#gpio-cells = <2>;
223*4882a593Smuzhiyun				interrupt-controller;
224*4882a593Smuzhiyun				#interrupt-cells = <2>;
225*4882a593Smuzhiyun			};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun			gpio3: gpio@1ac000 {
228*4882a593Smuzhiyun				compatible = "ti,omap4-gpio";
229*4882a593Smuzhiyun				ti,hwmods = "gpio3";
230*4882a593Smuzhiyun				ti,gpio-always-on;
231*4882a593Smuzhiyun				reg = <0x1ac000 0x2000>;
232*4882a593Smuzhiyun				interrupts = <32>;
233*4882a593Smuzhiyun				gpio-controller;
234*4882a593Smuzhiyun				#gpio-cells = <2>;
235*4882a593Smuzhiyun				interrupt-controller;
236*4882a593Smuzhiyun				#interrupt-cells = <2>;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun			gpio4: gpio@1ae000 {
240*4882a593Smuzhiyun				compatible = "ti,omap4-gpio";
241*4882a593Smuzhiyun				ti,hwmods = "gpio4";
242*4882a593Smuzhiyun				ti,gpio-always-on;
243*4882a593Smuzhiyun				reg = <0x1ae000 0x2000>;
244*4882a593Smuzhiyun				interrupts = <62>;
245*4882a593Smuzhiyun				gpio-controller;
246*4882a593Smuzhiyun				#gpio-cells = <2>;
247*4882a593Smuzhiyun				interrupt-controller;
248*4882a593Smuzhiyun				#interrupt-cells = <2>;
249*4882a593Smuzhiyun			};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun			i2c2: i2c@2a000 {
252*4882a593Smuzhiyun				compatible = "ti,omap4-i2c";
253*4882a593Smuzhiyun				#address-cells = <1>;
254*4882a593Smuzhiyun				#size-cells = <0>;
255*4882a593Smuzhiyun				ti,hwmods = "i2c2";
256*4882a593Smuzhiyun				reg = <0x2a000 0x1000>;
257*4882a593Smuzhiyun				interrupts = <71>;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun			mcspi1: spi@30000 {
261*4882a593Smuzhiyun				compatible = "ti,omap4-mcspi";
262*4882a593Smuzhiyun				reg = <0x30000 0x1000>;
263*4882a593Smuzhiyun				#address-cells = <1>;
264*4882a593Smuzhiyun				#size-cells = <0>;
265*4882a593Smuzhiyun				interrupts = <65>;
266*4882a593Smuzhiyun				ti,spi-num-cs = <4>;
267*4882a593Smuzhiyun				ti,hwmods = "mcspi1";
268*4882a593Smuzhiyun				dmas = <&edma 16 0 &edma 17 0
269*4882a593Smuzhiyun					&edma 18 0 &edma 19 0
270*4882a593Smuzhiyun					&edma 20 0 &edma 21 0
271*4882a593Smuzhiyun					&edma 22 0 &edma 23 0>;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun				dma-names = "tx0", "rx0", "tx1", "rx1",
274*4882a593Smuzhiyun					"tx2", "rx2", "tx3", "rx3";
275*4882a593Smuzhiyun			};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun			mcspi2: spi@1a0000 {
278*4882a593Smuzhiyun				compatible = "ti,omap4-mcspi";
279*4882a593Smuzhiyun				reg = <0x1a0000 0x1000>;
280*4882a593Smuzhiyun				#address-cells = <1>;
281*4882a593Smuzhiyun				#size-cells = <0>;
282*4882a593Smuzhiyun				interrupts = <125>;
283*4882a593Smuzhiyun				ti,spi-num-cs = <4>;
284*4882a593Smuzhiyun				ti,hwmods = "mcspi2";
285*4882a593Smuzhiyun				dmas = <&edma 42 0 &edma 43 0
286*4882a593Smuzhiyun					&edma 44 0 &edma 45 0>;
287*4882a593Smuzhiyun				dma-names = "tx0", "rx0", "tx1", "rx1";
288*4882a593Smuzhiyun			};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun			/* Board must configure dmas with edma_xbar for EDMA */
291*4882a593Smuzhiyun			mcspi3: spi@1a2000 {
292*4882a593Smuzhiyun				compatible = "ti,omap4-mcspi";
293*4882a593Smuzhiyun				reg = <0x1a2000 0x1000>;
294*4882a593Smuzhiyun				#address-cells = <1>;
295*4882a593Smuzhiyun				#size-cells = <0>;
296*4882a593Smuzhiyun				interrupts = <126>;
297*4882a593Smuzhiyun				ti,spi-num-cs = <4>;
298*4882a593Smuzhiyun				ti,hwmods = "mcspi3";
299*4882a593Smuzhiyun			};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun			mcspi4: spi@1a4000 {
302*4882a593Smuzhiyun				compatible = "ti,omap4-mcspi";
303*4882a593Smuzhiyun				reg = <0x1a4000 0x1000>;
304*4882a593Smuzhiyun				#address-cells = <1>;
305*4882a593Smuzhiyun				#size-cells = <0>;
306*4882a593Smuzhiyun				interrupts = <127>;
307*4882a593Smuzhiyun				ti,spi-num-cs = <4>;
308*4882a593Smuzhiyun				ti,hwmods = "mcspi4";
309*4882a593Smuzhiyun			};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun			timer1_target: target-module@2e000 {
312*4882a593Smuzhiyun				compatible = "ti,sysc-omap4-timer", "ti,sysc";
313*4882a593Smuzhiyun				reg = <0x2e000 0x4>,
314*4882a593Smuzhiyun				      <0x2e010 0x4>;
315*4882a593Smuzhiyun				reg-names = "rev", "sysc";
316*4882a593Smuzhiyun				ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
317*4882a593Smuzhiyun				ti,sysc-sidle = <SYSC_IDLE_FORCE>,
318*4882a593Smuzhiyun						<SYSC_IDLE_NO>,
319*4882a593Smuzhiyun						<SYSC_IDLE_SMART>,
320*4882a593Smuzhiyun						<SYSC_IDLE_SMART_WKUP>;
321*4882a593Smuzhiyun				clocks = <&timer1_fck>;
322*4882a593Smuzhiyun				clock-names = "fck";
323*4882a593Smuzhiyun				#address-cells = <1>;
324*4882a593Smuzhiyun				#size-cells = <1>;
325*4882a593Smuzhiyun				ranges = <0x0 0x2e000 0x1000>;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun				timer1: timer@0 {
328*4882a593Smuzhiyun					compatible = "ti,am335x-timer-1ms";
329*4882a593Smuzhiyun					reg = <0x0 0x400>;
330*4882a593Smuzhiyun					interrupts = <67>;
331*4882a593Smuzhiyun					ti,timer-alwon;
332*4882a593Smuzhiyun					clocks = <&timer1_fck>;
333*4882a593Smuzhiyun					clock-names = "fck";
334*4882a593Smuzhiyun				};
335*4882a593Smuzhiyun			};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun			uart1: uart@20000 {
338*4882a593Smuzhiyun				compatible = "ti,am3352-uart", "ti,omap3-uart";
339*4882a593Smuzhiyun				ti,hwmods = "uart1";
340*4882a593Smuzhiyun				reg = <0x20000 0x2000>;
341*4882a593Smuzhiyun				clock-frequency = <48000000>;
342*4882a593Smuzhiyun				interrupts = <72>;
343*4882a593Smuzhiyun				dmas = <&edma 26 0 &edma 27 0>;
344*4882a593Smuzhiyun				dma-names = "tx", "rx";
345*4882a593Smuzhiyun			};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun			uart2: uart@22000 {
348*4882a593Smuzhiyun				compatible = "ti,am3352-uart", "ti,omap3-uart";
349*4882a593Smuzhiyun				ti,hwmods = "uart2";
350*4882a593Smuzhiyun				reg = <0x22000 0x2000>;
351*4882a593Smuzhiyun				clock-frequency = <48000000>;
352*4882a593Smuzhiyun				interrupts = <73>;
353*4882a593Smuzhiyun				dmas = <&edma 28 0 &edma 29 0>;
354*4882a593Smuzhiyun				dma-names = "tx", "rx";
355*4882a593Smuzhiyun			};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun			uart3: uart@24000 {
358*4882a593Smuzhiyun				compatible = "ti,am3352-uart", "ti,omap3-uart";
359*4882a593Smuzhiyun				ti,hwmods = "uart3";
360*4882a593Smuzhiyun				reg = <0x24000 0x2000>;
361*4882a593Smuzhiyun				clock-frequency = <48000000>;
362*4882a593Smuzhiyun				interrupts = <74>;
363*4882a593Smuzhiyun				dmas = <&edma 30 0 &edma 31 0>;
364*4882a593Smuzhiyun				dma-names = "tx", "rx";
365*4882a593Smuzhiyun			};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun			timer2_target: target-module@40000 {
368*4882a593Smuzhiyun				compatible = "ti,sysc-omap4-timer", "ti,sysc";
369*4882a593Smuzhiyun				reg = <0x40000 0x4>,
370*4882a593Smuzhiyun				      <0x40010 0x4>;
371*4882a593Smuzhiyun				reg-names = "rev", "sysc";
372*4882a593Smuzhiyun				ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
373*4882a593Smuzhiyun				ti,sysc-sidle = <SYSC_IDLE_FORCE>,
374*4882a593Smuzhiyun						<SYSC_IDLE_NO>,
375*4882a593Smuzhiyun						<SYSC_IDLE_SMART>,
376*4882a593Smuzhiyun						<SYSC_IDLE_SMART_WKUP>;
377*4882a593Smuzhiyun				clocks = <&timer2_fck>;
378*4882a593Smuzhiyun				clock-names = "fck";
379*4882a593Smuzhiyun				#address-cells = <1>;
380*4882a593Smuzhiyun				#size-cells = <1>;
381*4882a593Smuzhiyun				ranges = <0x0 0x40000 0x1000>;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun				timer2: timer@0 {
384*4882a593Smuzhiyun					compatible = "ti,dm814-timer";
385*4882a593Smuzhiyun					reg = <0 0x1000>;
386*4882a593Smuzhiyun					interrupts = <68>;
387*4882a593Smuzhiyun					clocks = <&timer2_fck>;
388*4882a593Smuzhiyun					clock-names = "fck";
389*4882a593Smuzhiyun				};
390*4882a593Smuzhiyun			};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun			timer3: timer@42000 {
393*4882a593Smuzhiyun				compatible = "ti,dm814-timer";
394*4882a593Smuzhiyun				reg = <0x42000 0x2000>;
395*4882a593Smuzhiyun				interrupts = <69>;
396*4882a593Smuzhiyun				ti,hwmods = "timer3";
397*4882a593Smuzhiyun			};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun			mmc1: mmc@60000 {
400*4882a593Smuzhiyun				compatible = "ti,omap4-hsmmc";
401*4882a593Smuzhiyun				ti,hwmods = "mmc1";
402*4882a593Smuzhiyun				dmas = <&edma 24 0
403*4882a593Smuzhiyun					&edma 25 0>;
404*4882a593Smuzhiyun				dma-names = "tx", "rx";
405*4882a593Smuzhiyun				interrupts = <64>;
406*4882a593Smuzhiyun				interrupt-parent = <&intc>;
407*4882a593Smuzhiyun				reg = <0x60000 0x1000>;
408*4882a593Smuzhiyun			};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun			rtc: rtc@c0000 {
411*4882a593Smuzhiyun				compatible = "ti,am3352-rtc", "ti,da830-rtc";
412*4882a593Smuzhiyun				reg = <0xc0000 0x1000>;
413*4882a593Smuzhiyun				interrupts = <75 76>;
414*4882a593Smuzhiyun				ti,hwmods = "rtc";
415*4882a593Smuzhiyun			};
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun			mmc2: mmc@1d8000 {
418*4882a593Smuzhiyun				compatible = "ti,omap4-hsmmc";
419*4882a593Smuzhiyun				ti,hwmods = "mmc2";
420*4882a593Smuzhiyun				dmas = <&edma 2 0
421*4882a593Smuzhiyun					&edma 3 0>;
422*4882a593Smuzhiyun				dma-names = "tx", "rx";
423*4882a593Smuzhiyun				interrupts = <28>;
424*4882a593Smuzhiyun				interrupt-parent = <&intc>;
425*4882a593Smuzhiyun				reg = <0x1d8000 0x1000>;
426*4882a593Smuzhiyun			};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun			control: control@140000 {
429*4882a593Smuzhiyun				compatible = "ti,dm814-scm", "simple-bus";
430*4882a593Smuzhiyun				reg = <0x140000 0x20000>;
431*4882a593Smuzhiyun				#address-cells = <1>;
432*4882a593Smuzhiyun				#size-cells = <1>;
433*4882a593Smuzhiyun				ranges = <0 0x140000 0x20000>;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun				scm_conf: scm_conf@0 {
436*4882a593Smuzhiyun					compatible = "syscon", "simple-bus";
437*4882a593Smuzhiyun					reg = <0x0 0x800>;
438*4882a593Smuzhiyun					#address-cells = <1>;
439*4882a593Smuzhiyun					#size-cells = <1>;
440*4882a593Smuzhiyun					ranges = <0 0 0x800>;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun					phy_gmii_sel: phy-gmii-sel {
443*4882a593Smuzhiyun						compatible = "ti,dm814-phy-gmii-sel";
444*4882a593Smuzhiyun						reg = <0x650 0x4>;
445*4882a593Smuzhiyun						#phy-cells = <1>;
446*4882a593Smuzhiyun					};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun					scm_clocks: clocks {
449*4882a593Smuzhiyun						#address-cells = <1>;
450*4882a593Smuzhiyun						#size-cells = <0>;
451*4882a593Smuzhiyun					};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun					scm_clockdomains: clockdomains {
454*4882a593Smuzhiyun					};
455*4882a593Smuzhiyun				};
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun				usb_ctrl_mod: control@620 {
458*4882a593Smuzhiyun					compatible = "ti,am335x-usb-ctrl-module";
459*4882a593Smuzhiyun					reg = <0x620 0x10
460*4882a593Smuzhiyun						0x648 0x4>;
461*4882a593Smuzhiyun					reg-names = "phy_ctrl", "wakeup";
462*4882a593Smuzhiyun				};
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun				edma_xbar: dma-router@f90 {
465*4882a593Smuzhiyun					compatible = "ti,am335x-edma-crossbar";
466*4882a593Smuzhiyun					reg = <0xf90 0x40>;
467*4882a593Smuzhiyun					#dma-cells = <3>;
468*4882a593Smuzhiyun					dma-requests = <32>;
469*4882a593Smuzhiyun					dma-masters = <&edma>;
470*4882a593Smuzhiyun				};
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun				/*
473*4882a593Smuzhiyun				 * Note that silicon revision 2.1 and older
474*4882a593Smuzhiyun				 * require input enabled (bit 18 set) for all
475*4882a593Smuzhiyun				 * 3.3V I/Os to avoid cumulative hardware damage.
476*4882a593Smuzhiyun				 * For more info, see errata advisory 2.1.87.
477*4882a593Smuzhiyun				 * We leave bit 18 out of function-mask and rely
478*4882a593Smuzhiyun				 * on the bootloader for it.
479*4882a593Smuzhiyun				 */
480*4882a593Smuzhiyun				pincntl: pinmux@800 {
481*4882a593Smuzhiyun					compatible = "pinctrl-single";
482*4882a593Smuzhiyun					reg = <0x800 0x438>;
483*4882a593Smuzhiyun					#address-cells = <1>;
484*4882a593Smuzhiyun					#size-cells = <0>;
485*4882a593Smuzhiyun					#pinctrl-cells = <1>;
486*4882a593Smuzhiyun					pinctrl-single,register-width = <32>;
487*4882a593Smuzhiyun					pinctrl-single,function-mask = <0x307ff>;
488*4882a593Smuzhiyun				};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun				usb1_phy: usb-phy@1b00 {
491*4882a593Smuzhiyun					compatible = "ti,am335x-usb-phy";
492*4882a593Smuzhiyun					reg = <0x1b00 0x100>;
493*4882a593Smuzhiyun					reg-names = "phy";
494*4882a593Smuzhiyun					ti,ctrl_mod = <&usb_ctrl_mod>;
495*4882a593Smuzhiyun					#phy-cells = <0>;
496*4882a593Smuzhiyun				};
497*4882a593Smuzhiyun			};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun			prcm: prcm@180000 {
500*4882a593Smuzhiyun				compatible = "ti,dm814-prcm", "simple-bus";
501*4882a593Smuzhiyun				reg = <0x180000 0x2000>;
502*4882a593Smuzhiyun				#address-cells = <1>;
503*4882a593Smuzhiyun				#size-cells = <1>;
504*4882a593Smuzhiyun				ranges = <0 0x180000 0x2000>;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun				prcm_clocks: clocks {
507*4882a593Smuzhiyun					#address-cells = <1>;
508*4882a593Smuzhiyun					#size-cells = <0>;
509*4882a593Smuzhiyun				};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun				prcm_clockdomains: clockdomains {
512*4882a593Smuzhiyun				};
513*4882a593Smuzhiyun			};
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun			/* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */
516*4882a593Smuzhiyun			pllss: pllss@1c5000 {
517*4882a593Smuzhiyun				compatible = "ti,dm814-pllss", "simple-bus";
518*4882a593Smuzhiyun				reg = <0x1c5000 0x1000>;
519*4882a593Smuzhiyun				#address-cells = <1>;
520*4882a593Smuzhiyun				#size-cells = <1>;
521*4882a593Smuzhiyun				ranges = <0 0x1c5000 0x1000>;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun				pllss_clocks: clocks {
524*4882a593Smuzhiyun					#address-cells = <1>;
525*4882a593Smuzhiyun					#size-cells = <0>;
526*4882a593Smuzhiyun				};
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun				pllss_clockdomains: clockdomains {
529*4882a593Smuzhiyun				};
530*4882a593Smuzhiyun			};
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun			wdt1: wdt@1c7000 {
533*4882a593Smuzhiyun				compatible = "ti,omap3-wdt";
534*4882a593Smuzhiyun				ti,hwmods = "wd_timer";
535*4882a593Smuzhiyun				reg = <0x1c7000 0x1000>;
536*4882a593Smuzhiyun				interrupts = <91>;
537*4882a593Smuzhiyun			};
538*4882a593Smuzhiyun		};
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun		intc: interrupt-controller@48200000 {
541*4882a593Smuzhiyun			compatible = "ti,dm814-intc";
542*4882a593Smuzhiyun			interrupt-controller;
543*4882a593Smuzhiyun			#interrupt-cells = <1>;
544*4882a593Smuzhiyun			reg = <0x48200000 0x1000>;
545*4882a593Smuzhiyun		};
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun		/* Board must configure evtmux with edma_xbar for EDMA */
548*4882a593Smuzhiyun		mmc3: mmc@47810000 {
549*4882a593Smuzhiyun			compatible = "ti,omap4-hsmmc";
550*4882a593Smuzhiyun			ti,hwmods = "mmc3";
551*4882a593Smuzhiyun			interrupts = <29>;
552*4882a593Smuzhiyun			interrupt-parent = <&intc>;
553*4882a593Smuzhiyun			reg = <0x47810000 0x1000>;
554*4882a593Smuzhiyun		};
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun		target-module@49000000 {
557*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
558*4882a593Smuzhiyun			reg = <0x49000000 0x4>;
559*4882a593Smuzhiyun			reg-names = "rev";
560*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
561*4882a593Smuzhiyun			clock-names = "fck";
562*4882a593Smuzhiyun			#address-cells = <1>;
563*4882a593Smuzhiyun			#size-cells = <1>;
564*4882a593Smuzhiyun			ranges = <0x0 0x49000000 0x10000>;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun			edma: dma@0 {
567*4882a593Smuzhiyun				compatible = "ti,edma3-tpcc";
568*4882a593Smuzhiyun				reg = <0 0x10000>;
569*4882a593Smuzhiyun				reg-names = "edma3_cc";
570*4882a593Smuzhiyun				interrupts = <12 13 14>;
571*4882a593Smuzhiyun				interrupt-names = "edma3_ccint", "edma3_mperr",
572*4882a593Smuzhiyun						  "edma3_ccerrint";
573*4882a593Smuzhiyun				dma-requests = <64>;
574*4882a593Smuzhiyun				#dma-cells = <2>;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
577*4882a593Smuzhiyun					   <&edma_tptc2 3>, <&edma_tptc3 0>;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun				ti,edma-memcpy-channels = <20 21>;
580*4882a593Smuzhiyun			};
581*4882a593Smuzhiyun		};
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun		target-module@49800000 {
584*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
585*4882a593Smuzhiyun			reg = <0x49800000 0x4>,
586*4882a593Smuzhiyun			      <0x49800010 0x4>;
587*4882a593Smuzhiyun			reg-names = "rev", "sysc";
588*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
589*4882a593Smuzhiyun			ti,sysc-midle = <SYSC_IDLE_FORCE>;
590*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
591*4882a593Smuzhiyun					<SYSC_IDLE_SMART>;
592*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
593*4882a593Smuzhiyun			clock-names = "fck";
594*4882a593Smuzhiyun			#address-cells = <1>;
595*4882a593Smuzhiyun			#size-cells = <1>;
596*4882a593Smuzhiyun			ranges = <0x0 0x49800000 0x100000>;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun			edma_tptc0: dma@0 {
599*4882a593Smuzhiyun				compatible = "ti,edma3-tptc";
600*4882a593Smuzhiyun				reg = <0 0x100000>;
601*4882a593Smuzhiyun				interrupts = <112>;
602*4882a593Smuzhiyun				interrupt-names = "edma3_tcerrint";
603*4882a593Smuzhiyun			};
604*4882a593Smuzhiyun		};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun		target-module@49900000 {
607*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
608*4882a593Smuzhiyun			reg = <0x49900000 0x4>,
609*4882a593Smuzhiyun			      <0x49900010 0x4>;
610*4882a593Smuzhiyun			reg-names = "rev", "sysc";
611*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
612*4882a593Smuzhiyun			ti,sysc-midle = <SYSC_IDLE_FORCE>;
613*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
614*4882a593Smuzhiyun					<SYSC_IDLE_SMART>;
615*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
616*4882a593Smuzhiyun			clock-names = "fck";
617*4882a593Smuzhiyun			#address-cells = <1>;
618*4882a593Smuzhiyun			#size-cells = <1>;
619*4882a593Smuzhiyun			ranges = <0x0 0x49900000 0x100000>;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun			edma_tptc1: dma@0 {
622*4882a593Smuzhiyun				compatible = "ti,edma3-tptc";
623*4882a593Smuzhiyun				reg = <0 0x100000>;
624*4882a593Smuzhiyun				interrupts = <113>;
625*4882a593Smuzhiyun				interrupt-names = "edma3_tcerrint";
626*4882a593Smuzhiyun			};
627*4882a593Smuzhiyun		};
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun		target-module@49a00000 {
630*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
631*4882a593Smuzhiyun			reg = <0x49a00000 0x4>,
632*4882a593Smuzhiyun			      <0x49a00010 0x4>;
633*4882a593Smuzhiyun			reg-names = "rev", "sysc";
634*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
635*4882a593Smuzhiyun			ti,sysc-midle = <SYSC_IDLE_FORCE>;
636*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
637*4882a593Smuzhiyun					<SYSC_IDLE_SMART>;
638*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
639*4882a593Smuzhiyun			clock-names = "fck";
640*4882a593Smuzhiyun			#address-cells = <1>;
641*4882a593Smuzhiyun			#size-cells = <1>;
642*4882a593Smuzhiyun			ranges = <0x0 0x49a00000 0x100000>;
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun			edma_tptc2: dma@0 {
645*4882a593Smuzhiyun				compatible = "ti,edma3-tptc";
646*4882a593Smuzhiyun				reg = <0 0x100000>;
647*4882a593Smuzhiyun				interrupts = <114>;
648*4882a593Smuzhiyun				interrupt-names = "edma3_tcerrint";
649*4882a593Smuzhiyun			};
650*4882a593Smuzhiyun		};
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun		target-module@49b00000 {
653*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
654*4882a593Smuzhiyun			reg = <0x49b00000 0x4>,
655*4882a593Smuzhiyun			      <0x49b00010 0x4>;
656*4882a593Smuzhiyun			reg-names = "rev", "sysc";
657*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
658*4882a593Smuzhiyun			ti,sysc-midle = <SYSC_IDLE_FORCE>;
659*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
660*4882a593Smuzhiyun					<SYSC_IDLE_SMART>;
661*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
662*4882a593Smuzhiyun			clock-names = "fck";
663*4882a593Smuzhiyun			#address-cells = <1>;
664*4882a593Smuzhiyun			#size-cells = <1>;
665*4882a593Smuzhiyun			ranges = <0x0 0x49b00000 0x100000>;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun			edma_tptc3: dma@0 {
668*4882a593Smuzhiyun				compatible = "ti,edma3-tptc";
669*4882a593Smuzhiyun				reg = <0 0x100000>;
670*4882a593Smuzhiyun				interrupts = <115>;
671*4882a593Smuzhiyun				interrupt-names = "edma3_tcerrint";
672*4882a593Smuzhiyun			};
673*4882a593Smuzhiyun		};
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun		/* See TRM "Table 1-318. L4HS Instance Summary" */
676*4882a593Smuzhiyun		l4hs: l4hs@4a000000 {
677*4882a593Smuzhiyun			compatible = "ti,dm814-l4hs", "simple-bus";
678*4882a593Smuzhiyun			#address-cells = <1>;
679*4882a593Smuzhiyun			#size-cells = <1>;
680*4882a593Smuzhiyun			ranges = <0 0x4a000000 0x1b4040>;
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun			target-module@100000 {
683*4882a593Smuzhiyun				compatible = "ti,sysc-omap4-simple", "ti,sysc";
684*4882a593Smuzhiyun				reg = <0x100900 0x4>,
685*4882a593Smuzhiyun				      <0x100908 0x4>,
686*4882a593Smuzhiyun				      <0x100904 0x4>;
687*4882a593Smuzhiyun				reg-names = "rev", "sysc", "syss";
688*4882a593Smuzhiyun				ti,sysc-mask = <0>;
689*4882a593Smuzhiyun				ti,sysc-midle = <SYSC_IDLE_FORCE>,
690*4882a593Smuzhiyun						<SYSC_IDLE_NO>;
691*4882a593Smuzhiyun				ti,sysc-sidle = <SYSC_IDLE_FORCE>,
692*4882a593Smuzhiyun						<SYSC_IDLE_NO>;
693*4882a593Smuzhiyun				ti,syss-mask = <1>;
694*4882a593Smuzhiyun				clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
695*4882a593Smuzhiyun				clock-names = "fck";
696*4882a593Smuzhiyun				#address-cells = <1>;
697*4882a593Smuzhiyun				#size-cells = <1>;
698*4882a593Smuzhiyun				ranges = <0 0x100000 0x8000>;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun				mac: ethernet@0 {
701*4882a593Smuzhiyun					compatible = "ti,cpsw";
702*4882a593Smuzhiyun					clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
703*4882a593Smuzhiyun					clock-names = "fck", "cpts";
704*4882a593Smuzhiyun					cpdma_channels = <8>;
705*4882a593Smuzhiyun					ale_entries = <1024>;
706*4882a593Smuzhiyun					bd_ram_size = <0x2000>;
707*4882a593Smuzhiyun					mac_control = <0x20>;
708*4882a593Smuzhiyun					slaves = <2>;
709*4882a593Smuzhiyun					active_slave = <0>;
710*4882a593Smuzhiyun					cpts_clock_mult = <0x80000000>;
711*4882a593Smuzhiyun					cpts_clock_shift = <29>;
712*4882a593Smuzhiyun					reg = <0 0x800>,
713*4882a593Smuzhiyun					      <0x900 0x100>;
714*4882a593Smuzhiyun					#address-cells = <1>;
715*4882a593Smuzhiyun					#size-cells = <1>;
716*4882a593Smuzhiyun					/*
717*4882a593Smuzhiyun					* c0_rx_thresh_pend
718*4882a593Smuzhiyun					* c0_rx_pend
719*4882a593Smuzhiyun					* c0_tx_pend
720*4882a593Smuzhiyun					* c0_misc_pend
721*4882a593Smuzhiyun					*/
722*4882a593Smuzhiyun					interrupts = <40 41 42 43>;
723*4882a593Smuzhiyun					ranges = <0 0 0x8000>;
724*4882a593Smuzhiyun					syscon = <&scm_conf>;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun					davinci_mdio: mdio@800 {
727*4882a593Smuzhiyun						compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
728*4882a593Smuzhiyun						clocks = <&cpsw_125mhz_gclk>;
729*4882a593Smuzhiyun						clock-names = "fck";
730*4882a593Smuzhiyun						#address-cells = <1>;
731*4882a593Smuzhiyun						#size-cells = <0>;
732*4882a593Smuzhiyun						bus_freq = <1000000>;
733*4882a593Smuzhiyun						reg = <0x800 0x100>;
734*4882a593Smuzhiyun					};
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun					cpsw_emac0: slave@200 {
737*4882a593Smuzhiyun						/* Filled in by U-Boot */
738*4882a593Smuzhiyun						mac-address = [ 00 00 00 00 00 00 ];
739*4882a593Smuzhiyun						phys = <&phy_gmii_sel 1>;
740*4882a593Smuzhiyun					};
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun					cpsw_emac1: slave@300 {
743*4882a593Smuzhiyun						/* Filled in by U-Boot */
744*4882a593Smuzhiyun						mac-address = [ 00 00 00 00 00 00 ];
745*4882a593Smuzhiyun						phys = <&phy_gmii_sel 2>;
746*4882a593Smuzhiyun					};
747*4882a593Smuzhiyun				};
748*4882a593Smuzhiyun			};
749*4882a593Smuzhiyun		};
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun		gpmc: gpmc@50000000 {
752*4882a593Smuzhiyun			compatible = "ti,am3352-gpmc";
753*4882a593Smuzhiyun			ti,hwmods = "gpmc";
754*4882a593Smuzhiyun			ti,no-idle-on-init;
755*4882a593Smuzhiyun			reg = <0x50000000 0x2000>;
756*4882a593Smuzhiyun			interrupts = <100>;
757*4882a593Smuzhiyun			gpmc,num-cs = <7>;
758*4882a593Smuzhiyun			gpmc,num-waitpins = <2>;
759*4882a593Smuzhiyun			#address-cells = <2>;
760*4882a593Smuzhiyun			#size-cells = <1>;
761*4882a593Smuzhiyun			interrupt-controller;
762*4882a593Smuzhiyun			#interrupt-cells = <2>;
763*4882a593Smuzhiyun			gpio-controller;
764*4882a593Smuzhiyun			#gpio-cells = <2>;
765*4882a593Smuzhiyun		};
766*4882a593Smuzhiyun	};
767*4882a593Smuzhiyun};
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun#include "dm814x-clocks.dtsi"
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun/* Preferred always-on timer for clocksource */
772*4882a593Smuzhiyun&timer1_target {
773*4882a593Smuzhiyun	ti,no-reset-on-init;
774*4882a593Smuzhiyun	ti,no-idle;
775*4882a593Smuzhiyun	timer@0 {
776*4882a593Smuzhiyun		assigned-clocks = <&timer1_fck>;
777*4882a593Smuzhiyun		assigned-clock-parents = <&devosc_ck>;
778*4882a593Smuzhiyun	};
779*4882a593Smuzhiyun};
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun/* Preferred timer for clockevent */
782*4882a593Smuzhiyun&timer2_target {
783*4882a593Smuzhiyun	ti,no-reset-on-init;
784*4882a593Smuzhiyun	ti,no-idle;
785*4882a593Smuzhiyun	timer@0 {
786*4882a593Smuzhiyun		assigned-clocks = <&timer2_fck>;
787*4882a593Smuzhiyun		assigned-clock-parents = <&devosc_ck>;
788*4882a593Smuzhiyun	};
789*4882a593Smuzhiyun};
790