xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun&cbass_mcu_wakeup {
9*4882a593Smuzhiyun	dmsc: dmsc@44083000 {
10*4882a593Smuzhiyun		compatible = "ti,k2g-sci";
11*4882a593Smuzhiyun		ti,host-id = <12>;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun		mbox-names = "rx", "tx";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun		mboxes= <&secure_proxy_main 11>,
16*4882a593Smuzhiyun			<&secure_proxy_main 13>;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun		reg-names = "debug_messages";
19*4882a593Smuzhiyun		reg = <0x00 0x44083000 0x0 0x1000>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		k3_pds: power-controller {
22*4882a593Smuzhiyun			compatible = "ti,sci-pm-domain";
23*4882a593Smuzhiyun			#power-domain-cells = <2>;
24*4882a593Smuzhiyun		};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		k3_clks: clocks {
27*4882a593Smuzhiyun			compatible = "ti,k2g-sci-clk";
28*4882a593Smuzhiyun			#clock-cells = <2>;
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun		k3_reset: reset-controller {
32*4882a593Smuzhiyun			compatible = "ti,sci-reset";
33*4882a593Smuzhiyun			#reset-cells = <2>;
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	mcu_conf: syscon@40f00000 {
38*4882a593Smuzhiyun		compatible = "syscon", "simple-mfd";
39*4882a593Smuzhiyun		reg = <0x0 0x40f00000 0x0 0x20000>;
40*4882a593Smuzhiyun		#address-cells = <1>;
41*4882a593Smuzhiyun		#size-cells = <1>;
42*4882a593Smuzhiyun		ranges = <0x0 0x0 0x40f00000 0x20000>;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun		phy_gmii_sel: phy@4040 {
45*4882a593Smuzhiyun			compatible = "ti,am654-phy-gmii-sel";
46*4882a593Smuzhiyun			reg = <0x4040 0x4>;
47*4882a593Smuzhiyun			#phy-cells = <1>;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	chipid@43000014 {
52*4882a593Smuzhiyun		compatible = "ti,am654-chipid";
53*4882a593Smuzhiyun		reg = <0x0 0x43000014 0x0 0x4>;
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	wkup_pmx0: pinctrl@4301c000 {
57*4882a593Smuzhiyun		compatible = "pinctrl-single";
58*4882a593Smuzhiyun		/* Proxy 0 addressing */
59*4882a593Smuzhiyun		reg = <0x00 0x4301c000 0x00 0x178>;
60*4882a593Smuzhiyun		#pinctrl-cells = <1>;
61*4882a593Smuzhiyun		pinctrl-single,register-width = <32>;
62*4882a593Smuzhiyun		pinctrl-single,function-mask = <0xffffffff>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	mcu_ram: sram@41c00000 {
66*4882a593Smuzhiyun		compatible = "mmio-sram";
67*4882a593Smuzhiyun		reg = <0x00 0x41c00000 0x00 0x100000>;
68*4882a593Smuzhiyun		ranges = <0x0 0x00 0x41c00000 0x100000>;
69*4882a593Smuzhiyun		#address-cells = <1>;
70*4882a593Smuzhiyun		#size-cells = <1>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	wkup_uart0: serial@42300000 {
74*4882a593Smuzhiyun		compatible = "ti,j721e-uart", "ti,am654-uart";
75*4882a593Smuzhiyun		reg = <0x00 0x42300000 0x00 0x100>;
76*4882a593Smuzhiyun		reg-shift = <2>;
77*4882a593Smuzhiyun		reg-io-width = <4>;
78*4882a593Smuzhiyun		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
79*4882a593Smuzhiyun		clock-frequency = <48000000>;
80*4882a593Smuzhiyun		current-speed = <115200>;
81*4882a593Smuzhiyun		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
82*4882a593Smuzhiyun		clocks = <&k3_clks 287 0>;
83*4882a593Smuzhiyun		clock-names = "fclk";
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	mcu_uart0: serial@40a00000 {
87*4882a593Smuzhiyun		compatible = "ti,j721e-uart", "ti,am654-uart";
88*4882a593Smuzhiyun		reg = <0x00 0x40a00000 0x00 0x100>;
89*4882a593Smuzhiyun		reg-shift = <2>;
90*4882a593Smuzhiyun		reg-io-width = <4>;
91*4882a593Smuzhiyun		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
92*4882a593Smuzhiyun		clock-frequency = <96000000>;
93*4882a593Smuzhiyun		current-speed = <115200>;
94*4882a593Smuzhiyun		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
95*4882a593Smuzhiyun		clocks = <&k3_clks 149 0>;
96*4882a593Smuzhiyun		clock-names = "fclk";
97*4882a593Smuzhiyun	};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	wkup_gpio_intr: interrupt-controller2 {
100*4882a593Smuzhiyun		compatible = "ti,sci-intr";
101*4882a593Smuzhiyun		ti,intr-trigger-type = <1>;
102*4882a593Smuzhiyun		interrupt-controller;
103*4882a593Smuzhiyun		interrupt-parent = <&gic500>;
104*4882a593Smuzhiyun		#interrupt-cells = <1>;
105*4882a593Smuzhiyun		ti,sci = <&dmsc>;
106*4882a593Smuzhiyun		ti,sci-dev-id = <137>;
107*4882a593Smuzhiyun		ti,interrupt-ranges = <16 960 16>;
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	wkup_gpio0: gpio@42110000 {
111*4882a593Smuzhiyun		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
112*4882a593Smuzhiyun		reg = <0x0 0x42110000 0x0 0x100>;
113*4882a593Smuzhiyun		gpio-controller;
114*4882a593Smuzhiyun		#gpio-cells = <2>;
115*4882a593Smuzhiyun		interrupt-parent = <&wkup_gpio_intr>;
116*4882a593Smuzhiyun		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
117*4882a593Smuzhiyun		interrupt-controller;
118*4882a593Smuzhiyun		#interrupt-cells = <2>;
119*4882a593Smuzhiyun		ti,ngpio = <84>;
120*4882a593Smuzhiyun		ti,davinci-gpio-unbanked = <0>;
121*4882a593Smuzhiyun		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
122*4882a593Smuzhiyun		clocks = <&k3_clks 113 0>;
123*4882a593Smuzhiyun		clock-names = "gpio";
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	wkup_gpio1: gpio@42100000 {
127*4882a593Smuzhiyun		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
128*4882a593Smuzhiyun		reg = <0x0 0x42100000 0x0 0x100>;
129*4882a593Smuzhiyun		gpio-controller;
130*4882a593Smuzhiyun		#gpio-cells = <2>;
131*4882a593Smuzhiyun		interrupt-parent = <&wkup_gpio_intr>;
132*4882a593Smuzhiyun		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
133*4882a593Smuzhiyun		interrupt-controller;
134*4882a593Smuzhiyun		#interrupt-cells = <2>;
135*4882a593Smuzhiyun		ti,ngpio = <84>;
136*4882a593Smuzhiyun		ti,davinci-gpio-unbanked = <0>;
137*4882a593Smuzhiyun		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
138*4882a593Smuzhiyun		clocks = <&k3_clks 114 0>;
139*4882a593Smuzhiyun		clock-names = "gpio";
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	mcu_i2c0: i2c@40b00000 {
143*4882a593Smuzhiyun		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
144*4882a593Smuzhiyun		reg = <0x0 0x40b00000 0x0 0x100>;
145*4882a593Smuzhiyun		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
146*4882a593Smuzhiyun		#address-cells = <1>;
147*4882a593Smuzhiyun		#size-cells = <0>;
148*4882a593Smuzhiyun		clock-names = "fck";
149*4882a593Smuzhiyun		clocks = <&k3_clks 194 0>;
150*4882a593Smuzhiyun		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
151*4882a593Smuzhiyun	};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun	mcu_i2c1: i2c@40b10000 {
154*4882a593Smuzhiyun		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
155*4882a593Smuzhiyun		reg = <0x0 0x40b10000 0x0 0x100>;
156*4882a593Smuzhiyun		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
157*4882a593Smuzhiyun		#address-cells = <1>;
158*4882a593Smuzhiyun		#size-cells = <0>;
159*4882a593Smuzhiyun		clock-names = "fck";
160*4882a593Smuzhiyun		clocks = <&k3_clks 195 0>;
161*4882a593Smuzhiyun		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
162*4882a593Smuzhiyun	};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun	wkup_i2c0: i2c@42120000 {
165*4882a593Smuzhiyun		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
166*4882a593Smuzhiyun		reg = <0x0 0x42120000 0x0 0x100>;
167*4882a593Smuzhiyun		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
168*4882a593Smuzhiyun		#address-cells = <1>;
169*4882a593Smuzhiyun		#size-cells = <0>;
170*4882a593Smuzhiyun		clock-names = "fck";
171*4882a593Smuzhiyun		clocks = <&k3_clks 197 0>;
172*4882a593Smuzhiyun		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun	fss: fss@47000000 {
176*4882a593Smuzhiyun		compatible = "simple-bus";
177*4882a593Smuzhiyun		reg = <0x0 0x47000000 0x0 0x100>;
178*4882a593Smuzhiyun		#address-cells = <2>;
179*4882a593Smuzhiyun		#size-cells = <2>;
180*4882a593Smuzhiyun		ranges;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		ospi0: spi@47040000 {
183*4882a593Smuzhiyun			compatible = "ti,am654-ospi";
184*4882a593Smuzhiyun			reg = <0x0 0x47040000 0x0 0x100>,
185*4882a593Smuzhiyun				<0x5 0x00000000 0x1 0x0000000>;
186*4882a593Smuzhiyun			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
187*4882a593Smuzhiyun			cdns,fifo-depth = <256>;
188*4882a593Smuzhiyun			cdns,fifo-width = <4>;
189*4882a593Smuzhiyun			cdns,trigger-address = <0x0>;
190*4882a593Smuzhiyun			clocks = <&k3_clks 103 0>;
191*4882a593Smuzhiyun			assigned-clocks = <&k3_clks 103 0>;
192*4882a593Smuzhiyun			assigned-clock-parents = <&k3_clks 103 2>;
193*4882a593Smuzhiyun			assigned-clock-rates = <166666666>;
194*4882a593Smuzhiyun			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
195*4882a593Smuzhiyun			#address-cells = <1>;
196*4882a593Smuzhiyun			#size-cells = <0>;
197*4882a593Smuzhiyun		};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun		ospi1: spi@47050000 {
200*4882a593Smuzhiyun			compatible = "ti,am654-ospi";
201*4882a593Smuzhiyun			reg = <0x0 0x47050000 0x0 0x100>,
202*4882a593Smuzhiyun				<0x7 0x00000000 0x1 0x00000000>;
203*4882a593Smuzhiyun			interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
204*4882a593Smuzhiyun			cdns,fifo-depth = <256>;
205*4882a593Smuzhiyun			cdns,fifo-width = <4>;
206*4882a593Smuzhiyun			cdns,trigger-address = <0x0>;
207*4882a593Smuzhiyun			clocks = <&k3_clks 104 0>;
208*4882a593Smuzhiyun			power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
209*4882a593Smuzhiyun			#address-cells = <1>;
210*4882a593Smuzhiyun			#size-cells = <0>;
211*4882a593Smuzhiyun		};
212*4882a593Smuzhiyun	};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun	tscadc0: tscadc@40200000 {
215*4882a593Smuzhiyun		compatible = "ti,am3359-tscadc";
216*4882a593Smuzhiyun		reg = <0x0 0x40200000 0x0 0x1000>;
217*4882a593Smuzhiyun		interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
218*4882a593Smuzhiyun		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
219*4882a593Smuzhiyun		clocks = <&k3_clks 0 1>;
220*4882a593Smuzhiyun		assigned-clocks = <&k3_clks 0 3>;
221*4882a593Smuzhiyun		assigned-clock-rates = <60000000>;
222*4882a593Smuzhiyun		clock-names = "adc_tsc_fck";
223*4882a593Smuzhiyun		dmas = <&main_udmap 0x7400>,
224*4882a593Smuzhiyun			<&main_udmap 0x7401>;
225*4882a593Smuzhiyun		dma-names = "fifo0", "fifo1";
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun		adc {
228*4882a593Smuzhiyun			#io-channel-cells = <1>;
229*4882a593Smuzhiyun			compatible = "ti,am3359-adc";
230*4882a593Smuzhiyun		};
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	tscadc1: tscadc@40210000 {
234*4882a593Smuzhiyun		compatible = "ti,am3359-tscadc";
235*4882a593Smuzhiyun		reg = <0x0 0x40210000 0x0 0x1000>;
236*4882a593Smuzhiyun		interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
237*4882a593Smuzhiyun		power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
238*4882a593Smuzhiyun		clocks = <&k3_clks 1 1>;
239*4882a593Smuzhiyun		assigned-clocks = <&k3_clks 1 3>;
240*4882a593Smuzhiyun		assigned-clock-rates = <60000000>;
241*4882a593Smuzhiyun		clock-names = "adc_tsc_fck";
242*4882a593Smuzhiyun		dmas = <&main_udmap 0x7402>,
243*4882a593Smuzhiyun			<&main_udmap 0x7403>;
244*4882a593Smuzhiyun		dma-names = "fifo0", "fifo1";
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun		adc {
247*4882a593Smuzhiyun			#io-channel-cells = <1>;
248*4882a593Smuzhiyun			compatible = "ti,am3359-adc";
249*4882a593Smuzhiyun		};
250*4882a593Smuzhiyun	};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun	mcu-navss {
253*4882a593Smuzhiyun		compatible = "simple-mfd";
254*4882a593Smuzhiyun		#address-cells = <2>;
255*4882a593Smuzhiyun		#size-cells = <2>;
256*4882a593Smuzhiyun		ranges;
257*4882a593Smuzhiyun		dma-coherent;
258*4882a593Smuzhiyun		dma-ranges;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun		ti,sci-dev-id = <232>;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun		mcu_ringacc: ringacc@2b800000 {
263*4882a593Smuzhiyun			compatible = "ti,am654-navss-ringacc";
264*4882a593Smuzhiyun			reg =	<0x0 0x2b800000 0x0 0x400000>,
265*4882a593Smuzhiyun				<0x0 0x2b000000 0x0 0x400000>,
266*4882a593Smuzhiyun				<0x0 0x28590000 0x0 0x100>,
267*4882a593Smuzhiyun				<0x0 0x2a500000 0x0 0x40000>;
268*4882a593Smuzhiyun			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
269*4882a593Smuzhiyun			ti,num-rings = <286>;
270*4882a593Smuzhiyun			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
271*4882a593Smuzhiyun			ti,sci = <&dmsc>;
272*4882a593Smuzhiyun			ti,sci-dev-id = <235>;
273*4882a593Smuzhiyun			msi-parent = <&main_udmass_inta>;
274*4882a593Smuzhiyun		};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun		mcu_udmap: dma-controller@285c0000 {
277*4882a593Smuzhiyun			compatible = "ti,j721e-navss-mcu-udmap";
278*4882a593Smuzhiyun			reg =	<0x0 0x285c0000 0x0 0x100>,
279*4882a593Smuzhiyun				<0x0 0x2a800000 0x0 0x40000>,
280*4882a593Smuzhiyun				<0x0 0x2aa00000 0x0 0x40000>;
281*4882a593Smuzhiyun			reg-names = "gcfg", "rchanrt", "tchanrt";
282*4882a593Smuzhiyun			msi-parent = <&main_udmass_inta>;
283*4882a593Smuzhiyun			#dma-cells = <1>;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun			ti,sci = <&dmsc>;
286*4882a593Smuzhiyun			ti,sci-dev-id = <236>;
287*4882a593Smuzhiyun			ti,ringacc = <&mcu_ringacc>;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
290*4882a593Smuzhiyun						<0x0f>; /* TX_HCHAN */
291*4882a593Smuzhiyun			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
292*4882a593Smuzhiyun						<0x0b>; /* RX_HCHAN */
293*4882a593Smuzhiyun			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun	};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun	mcu_cpsw: ethernet@46000000 {
298*4882a593Smuzhiyun		compatible = "ti,j721e-cpsw-nuss";
299*4882a593Smuzhiyun		#address-cells = <2>;
300*4882a593Smuzhiyun		#size-cells = <2>;
301*4882a593Smuzhiyun		reg = <0x0 0x46000000 0x0 0x200000>;
302*4882a593Smuzhiyun		reg-names = "cpsw_nuss";
303*4882a593Smuzhiyun		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
304*4882a593Smuzhiyun		dma-coherent;
305*4882a593Smuzhiyun		clocks = <&k3_clks 18 22>;
306*4882a593Smuzhiyun		clock-names = "fck";
307*4882a593Smuzhiyun		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun		dmas = <&mcu_udmap 0xf000>,
310*4882a593Smuzhiyun		       <&mcu_udmap 0xf001>,
311*4882a593Smuzhiyun		       <&mcu_udmap 0xf002>,
312*4882a593Smuzhiyun		       <&mcu_udmap 0xf003>,
313*4882a593Smuzhiyun		       <&mcu_udmap 0xf004>,
314*4882a593Smuzhiyun		       <&mcu_udmap 0xf005>,
315*4882a593Smuzhiyun		       <&mcu_udmap 0xf006>,
316*4882a593Smuzhiyun		       <&mcu_udmap 0xf007>,
317*4882a593Smuzhiyun		       <&mcu_udmap 0x7000>;
318*4882a593Smuzhiyun		dma-names = "tx0", "tx1", "tx2", "tx3",
319*4882a593Smuzhiyun			    "tx4", "tx5", "tx6", "tx7",
320*4882a593Smuzhiyun			    "rx";
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun		ethernet-ports {
323*4882a593Smuzhiyun			#address-cells = <1>;
324*4882a593Smuzhiyun			#size-cells = <0>;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun			cpsw_port1: port@1 {
327*4882a593Smuzhiyun				reg = <1>;
328*4882a593Smuzhiyun				ti,mac-only;
329*4882a593Smuzhiyun				label = "port1";
330*4882a593Smuzhiyun				ti,syscon-efuse = <&mcu_conf 0x200>;
331*4882a593Smuzhiyun				phys = <&phy_gmii_sel 1>;
332*4882a593Smuzhiyun			};
333*4882a593Smuzhiyun		};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun		davinci_mdio: mdio@f00 {
336*4882a593Smuzhiyun			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
337*4882a593Smuzhiyun			reg = <0x0 0xf00 0x0 0x100>;
338*4882a593Smuzhiyun			#address-cells = <1>;
339*4882a593Smuzhiyun			#size-cells = <0>;
340*4882a593Smuzhiyun			clocks = <&k3_clks 18 22>;
341*4882a593Smuzhiyun			clock-names = "fck";
342*4882a593Smuzhiyun			bus_freq = <1000000>;
343*4882a593Smuzhiyun		};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun		cpts@3d000 {
346*4882a593Smuzhiyun			compatible = "ti,am65-cpts";
347*4882a593Smuzhiyun			reg = <0x0 0x3d000 0x0 0x400>;
348*4882a593Smuzhiyun			clocks = <&k3_clks 18 2>;
349*4882a593Smuzhiyun			clock-names = "cpts";
350*4882a593Smuzhiyun			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
351*4882a593Smuzhiyun			interrupt-names = "cpts";
352*4882a593Smuzhiyun			ti,cpts-ext-ts-inputs = <4>;
353*4882a593Smuzhiyun			ti,cpts-periodic-outputs = <2>;
354*4882a593Smuzhiyun		};
355*4882a593Smuzhiyun	};
356*4882a593Smuzhiyun};
357