Lines Matching +full:cpsw +full:- +full:mdio
2 * CPSW Ethernet Switch Driver
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
23 #include <cpsw.h>
34 #define BITMASK(bits) (BIT(bits) - 1)
83 * This timeout definition is a worst-case ultra defensive measure against
200 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
240 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
241 #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
242 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
244 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
245 #define chan_read(chan, fld) __raw_readl((chan)->fld)
246 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
249 slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
251 for (slave = (priv)->slaves; slave != (priv)->slaves + \
252 (priv)->data.slaves; slave++)
284 start -= idx * 32; in cpsw_ale_get_field()
285 idx = 2 - idx; /* flip */ in cpsw_ale_get_field()
296 start -= idx * 32; in cpsw_ale_set_field()
297 idx = 2 - idx; /* flip */ in cpsw_ale_set_field()
327 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); in cpsw_ale_get_addr()
335 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); in cpsw_ale_set_addr()
342 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); in cpsw_ale_read()
345 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); in cpsw_ale_read()
355 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); in cpsw_ale_write()
357 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); in cpsw_ale_write()
367 for (idx = 0; idx < priv->data.ale_entries; idx++) { in cpsw_ale_match_addr()
378 return -ENOENT; in cpsw_ale_match_addr()
386 for (idx = 0; idx < priv->data.ale_entries; idx++) { in cpsw_ale_match_free()
392 return -ENOENT; in cpsw_ale_match_free()
400 for (idx = 0; idx < priv->data.ale_entries; idx++) { in cpsw_ale_find_ageable()
412 return -ENOENT; in cpsw_ale_find_ageable()
434 return -ENOMEM; in cpsw_ale_add_ucast()
463 return -ENOMEM; in cpsw_ale_add_mcast()
473 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); in cpsw_ale_control()
476 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); in cpsw_ale_control()
489 tmp = __raw_readl(priv->ale_regs + offset); in cpsw_ale_port_state()
492 __raw_writel(tmp, priv->ale_regs + offset); in cpsw_ale_port_state()
503 while (timeout-- && in wait_for_user_access()
504 ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) in wait_for_user_access()
507 if (timeout == -1) { in wait_for_user_access()
509 return -ETIMEDOUT; in wait_for_user_access()
519 while (timeout-- && in wait_for_idle()
520 ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) in wait_for_idle()
523 if (timeout == -1) in wait_for_idle()
534 return -EINVAL; in cpsw_mdio_read()
539 __raw_writel(reg, &mdio_regs->user[0].access); in cpsw_mdio_read()
542 data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; in cpsw_mdio_read()
552 return -EINVAL; in cpsw_mdio_write()
557 __raw_writel(reg, &mdio_regs->user[0].access); in cpsw_mdio_write()
570 __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); in cpsw_mdio_init()
582 bus->read = cpsw_mdio_read; in cpsw_mdio_init()
583 bus->write = cpsw_mdio_write; in cpsw_mdio_init()
584 strcpy(bus->name, name); in cpsw_mdio_init()
589 /* Set a self-clearing bit in a register, and wait for it to clear */
605 struct eth_pdata *pdata = dev_get_platdata(priv->dev); in cpsw_set_slave_mac()
607 writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi); in cpsw_set_slave_mac()
608 writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo); in cpsw_set_slave_mac()
610 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); in cpsw_set_slave_mac()
611 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); in cpsw_set_slave_mac()
620 int ret = -ENODEV; in cpsw_slave_update_link()
622 phy = priv->phydev; in cpsw_slave_update_link()
631 *link = phy->link; in cpsw_slave_update_link()
633 if (phy->link) { /* link up */ in cpsw_slave_update_link()
634 mac_control = priv->data.mac_control; in cpsw_slave_update_link()
635 if (phy->speed == 1000) in cpsw_slave_update_link()
637 if (phy->duplex == DUPLEX_FULL) in cpsw_slave_update_link()
639 if (phy->speed == 100) in cpsw_slave_update_link()
643 if (mac_control == slave->mac_control) in cpsw_slave_update_link()
648 slave->slave_num, phy->speed, in cpsw_slave_update_link()
649 (phy->duplex == DUPLEX_FULL) ? "full" : "half"); in cpsw_slave_update_link()
651 printf("link down on port %d\n", slave->slave_num); in cpsw_slave_update_link()
654 __raw_writel(mac_control, &slave->sliver->mac_control); in cpsw_slave_update_link()
655 slave->mac_control = mac_control; in cpsw_slave_update_link()
663 int ret = -ENODEV; in cpsw_update_link()
674 if (priv->host_port == 0) in cpsw_get_slave_port()
684 setbit_and_wait_for_clear32(&slave->sliver->soft_reset); in cpsw_slave_init()
687 __raw_writel(0x76543210, &slave->sliver->rx_pri_map); in cpsw_slave_init()
688 __raw_writel(0x33221100, &slave->regs->tx_pri_map); in cpsw_slave_init()
691 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); in cpsw_slave_init()
694 slave->mac_control = 0; /* no link yet */ in cpsw_slave_init()
697 slave_port = cpsw_get_slave_port(priv, slave->slave_num); in cpsw_slave_init()
702 priv->phy_mask |= 1 << slave->data->phy_addr; in cpsw_slave_init()
707 struct cpdma_desc *desc = priv->desc_free; in cpdma_desc_alloc()
710 priv->desc_free = desc_read_ptr(desc, hw_next); in cpdma_desc_alloc()
717 desc_write(desc, hw_next, priv->desc_free); in cpdma_desc_free()
718 priv->desc_free = desc; in cpdma_desc_free()
730 return -ENOMEM; in cpdma_submit()
744 if (!chan->head) { in cpdma_submit()
745 /* simple case - first packet enqueued */ in cpdma_submit()
746 chan->head = desc; in cpdma_submit()
747 chan->tail = desc; in cpdma_submit()
752 /* not the first packet - enqueue at the tail */ in cpdma_submit()
753 prev = chan->tail; in cpdma_submit()
755 chan->tail = desc; in cpdma_submit()
762 if (chan->rxfree) in cpdma_submit()
770 struct cpdma_desc *desc = chan->head; in cpdma_process()
774 return -ENOENT; in cpdma_process()
790 return -EBUSY; in cpdma_process()
793 chan->head = desc_read_ptr(desc, hw_next); in cpdma_process()
806 setbit_and_wait_for_clear32(&priv->regs->soft_reset); in _cpsw_init()
814 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); in _cpsw_init()
815 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); in _cpsw_init()
818 __raw_writel(0, &priv->regs->ptype); in _cpsw_init()
821 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); in _cpsw_init()
822 __raw_writel(0x7, &priv->regs->stat_port_en); in _cpsw_init()
824 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); in _cpsw_init()
826 cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE); in _cpsw_init()
827 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port); in _cpsw_init()
838 desc_write(&priv->descs[i], hw_next, in _cpsw_init()
839 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); in _cpsw_init()
841 priv->desc_free = &priv->descs[0]; in _cpsw_init()
844 if (priv->data.version == CPSW_CTRL_VERSION_2) { in _cpsw_init()
845 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); in _cpsw_init()
846 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; in _cpsw_init()
847 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; in _cpsw_init()
848 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; in _cpsw_init()
850 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); in _cpsw_init()
851 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; in _cpsw_init()
852 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; in _cpsw_init()
854 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); in _cpsw_init()
855 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; in _cpsw_init()
856 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; in _cpsw_init()
857 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; in _cpsw_init()
859 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); in _cpsw_init()
860 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; in _cpsw_init()
861 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; in _cpsw_init()
865 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); in _cpsw_init()
867 if (priv->data.version == CPSW_CTRL_VERSION_2) { in _cpsw_init()
868 for (i = 0; i < priv->data.channels; i++) { in _cpsw_init()
869 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 in _cpsw_init()
871 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 in _cpsw_init()
873 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 in _cpsw_init()
875 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 in _cpsw_init()
877 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 in _cpsw_init()
881 for (i = 0; i < priv->data.channels; i++) { in _cpsw_init()
882 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 in _cpsw_init()
884 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 in _cpsw_init()
886 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 in _cpsw_init()
888 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 in _cpsw_init()
890 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 in _cpsw_init()
896 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); in _cpsw_init()
897 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); in _cpsw_init()
901 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i], in _cpsw_init()
915 writel(0, priv->dma_regs + CPDMA_TXCONTROL); in _cpsw_halt()
916 writel(0, priv->dma_regs + CPDMA_RXCONTROL); in _cpsw_halt()
919 setbit_and_wait_for_clear32(&priv->regs->soft_reset); in _cpsw_halt()
922 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); in _cpsw_halt()
936 while (timeout-- && in _cpsw_send()
937 (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0)) in _cpsw_send()
940 if (timeout == -1) { in _cpsw_send()
942 return -ETIMEDOUT; in _cpsw_send()
945 return cpdma_submit(priv, &priv->tx_chan, packet, length); in _cpsw_send()
952 int ret = -EAGAIN; in _cpsw_recv()
954 ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len); in _cpsw_recv()
968 void *regs = priv->regs; in cpsw_slave_setup()
969 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; in cpsw_slave_setup()
970 slave->slave_num = slave_num; in cpsw_slave_setup()
971 slave->data = data; in cpsw_slave_setup()
972 slave->regs = regs + data->slave_reg_ofs; in cpsw_slave_setup()
973 slave->sliver = regs + data->sliver_reg_ofs; in cpsw_slave_setup()
981 phydev = phy_connect(priv->bus, in cpsw_phy_init()
982 slave->data->phy_addr, in cpsw_phy_init()
983 priv->dev, in cpsw_phy_init()
984 slave->data->phy_if); in cpsw_phy_init()
987 return -1; in cpsw_phy_init()
989 phydev->supported &= supported; in cpsw_phy_init()
990 phydev->advertising = phydev->supported; in cpsw_phy_init()
993 if (slave->data->phy_of_handle) in cpsw_phy_init()
994 dev_set_of_offset(phydev->dev, slave->data->phy_of_handle); in cpsw_phy_init()
997 priv->phydev = phydev; in cpsw_phy_init()
1006 struct cpsw_platform_data *data = &priv->data; in _cpsw_register()
1007 void *regs = (void *)data->cpsw_base; in _cpsw_register()
1009 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); in _cpsw_register()
1010 if (!priv->slaves) { in _cpsw_register()
1011 return -ENOMEM; in _cpsw_register()
1014 priv->host_port = data->host_port_num; in _cpsw_register()
1015 priv->regs = regs; in _cpsw_register()
1016 priv->host_port_regs = regs + data->host_port_reg_ofs; in _cpsw_register()
1017 priv->dma_regs = regs + data->cpdma_reg_ofs; in _cpsw_register()
1018 priv->ale_regs = regs + data->ale_reg_ofs; in _cpsw_register()
1019 priv->descs = (void *)regs + data->bd_ram_ofs; in _cpsw_register()
1028 cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div); in _cpsw_register()
1029 priv->bus = miiphy_get_dev_by_name(priv->dev->name); in _cpsw_register()
1039 struct cpsw_priv *priv = dev->priv; in cpsw_init()
1041 return _cpsw_init(priv, dev->enetaddr); in cpsw_init()
1046 struct cpsw_priv *priv = dev->priv; in cpsw_halt()
1053 struct cpsw_priv *priv = dev->priv; in cpsw_send()
1060 struct cpsw_priv *priv = dev->priv; in cpsw_recv()
1068 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE); in cpsw_recv()
1082 return -ENOMEM; in cpsw_register()
1087 return -ENOMEM; in cpsw_register()
1090 priv->dev = dev; in cpsw_register()
1091 priv->data = *data; in cpsw_register()
1093 strcpy(dev->name, "cpsw"); in cpsw_register()
1094 dev->iobase = 0; in cpsw_register()
1095 dev->init = cpsw_init; in cpsw_register()
1096 dev->halt = cpsw_halt; in cpsw_register()
1097 dev->send = cpsw_send; in cpsw_register()
1098 dev->recv = cpsw_recv; in cpsw_register()
1099 dev->priv = priv; in cpsw_register()
1119 return _cpsw_init(priv, pdata->enetaddr); in cpsw_eth_start()
1141 return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE); in cpsw_eth_free_pkt()
1156 priv->dev = dev; in cpsw_eth_probe()
1182 int slave = priv->data.active_slave; in cpsw_gmii_sel_am3352()
1184 reg = readl(priv->data.gmii_sel); in cpsw_gmii_sel_am3352()
1210 if (priv->data.rmii_clock_external) { in cpsw_gmii_sel_am3352()
1227 writel(reg, priv->data.gmii_sel); in cpsw_gmii_sel_am3352()
1236 int slave = priv->data.active_slave; in cpsw_gmii_sel_dra7xx()
1238 reg = readl(priv->data.gmii_sel); in cpsw_gmii_sel_dra7xx()
1267 dev_err(priv->dev, "invalid slave number...\n"); in cpsw_gmii_sel_dra7xx()
1271 if (priv->data.rmii_clock_external) in cpsw_gmii_sel_dra7xx()
1272 dev_err(priv->dev, "RMII External clock is not supported\n"); in cpsw_gmii_sel_dra7xx()
1277 writel(reg, priv->data.gmii_sel); in cpsw_gmii_sel_dra7xx()
1283 if (!strcmp(compat, "ti,am3352-cpsw-phy-sel")) in cpsw_phy_sel()
1285 if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel")) in cpsw_phy_sel()
1287 else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel")) in cpsw_phy_sel()
1298 const void *fdt = gd->fdt_blob; in cpsw_eth_ofdata_to_platdata()
1306 pdata->iobase = devfdt_get_addr(dev); in cpsw_eth_ofdata_to_platdata()
1307 priv->data.version = CPSW_CTRL_VERSION_2; in cpsw_eth_ofdata_to_platdata()
1308 priv->data.bd_ram_ofs = CPSW_BD_OFFSET; in cpsw_eth_ofdata_to_platdata()
1309 priv->data.ale_reg_ofs = CPSW_ALE_OFFSET; in cpsw_eth_ofdata_to_platdata()
1310 priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET; in cpsw_eth_ofdata_to_platdata()
1311 priv->data.mdio_div = CPSW_MDIO_DIV; in cpsw_eth_ofdata_to_platdata()
1312 priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, in cpsw_eth_ofdata_to_platdata()
1314 pdata->phy_interface = -1; in cpsw_eth_ofdata_to_platdata()
1316 priv->data.cpsw_base = pdata->iobase; in cpsw_eth_ofdata_to_platdata()
1317 priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1); in cpsw_eth_ofdata_to_platdata()
1318 if (priv->data.channels <= 0) { in cpsw_eth_ofdata_to_platdata()
1320 return -ENOENT; in cpsw_eth_ofdata_to_platdata()
1323 priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1); in cpsw_eth_ofdata_to_platdata()
1324 if (priv->data.slaves <= 0) { in cpsw_eth_ofdata_to_platdata()
1326 return -ENOENT; in cpsw_eth_ofdata_to_platdata()
1328 priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) * in cpsw_eth_ofdata_to_platdata()
1329 priv->data.slaves); in cpsw_eth_ofdata_to_platdata()
1331 priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1); in cpsw_eth_ofdata_to_platdata()
1332 if (priv->data.ale_entries <= 0) { in cpsw_eth_ofdata_to_platdata()
1334 return -ENOENT; in cpsw_eth_ofdata_to_platdata()
1337 priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1); in cpsw_eth_ofdata_to_platdata()
1338 if (priv->data.bd_ram_ofs <= 0) { in cpsw_eth_ofdata_to_platdata()
1340 return -ENOENT; in cpsw_eth_ofdata_to_platdata()
1343 priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1); in cpsw_eth_ofdata_to_platdata()
1344 if (priv->data.mac_control <= 0) { in cpsw_eth_ofdata_to_platdata()
1346 return -ENOENT; in cpsw_eth_ofdata_to_platdata()
1349 num_mode_gpios = gpio_get_list_count(dev, "mode-gpios"); in cpsw_eth_ofdata_to_platdata()
1353 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios, in cpsw_eth_ofdata_to_platdata()
1359 priv->data.active_slave = active_slave; in cpsw_eth_ofdata_to_platdata()
1366 if (!strncmp(name, "mdio", 4)) { in cpsw_eth_ofdata_to_platdata()
1371 pr_err("Not able to get MDIO address space\n"); in cpsw_eth_ofdata_to_platdata()
1372 return -ENOENT; in cpsw_eth_ofdata_to_platdata()
1374 priv->data.mdio_base = mdio_base; in cpsw_eth_ofdata_to_platdata()
1380 if (slave_index >= priv->data.slaves) in cpsw_eth_ofdata_to_platdata()
1382 phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL); in cpsw_eth_ofdata_to_platdata()
1384 priv->data.slave_data[slave_index].phy_if = in cpsw_eth_ofdata_to_platdata()
1387 priv->data.slave_data[slave_index].phy_of_handle = in cpsw_eth_ofdata_to_platdata()
1389 "phy-handle"); in cpsw_eth_ofdata_to_platdata()
1391 if (priv->data.slave_data[slave_index].phy_of_handle >= 0) { in cpsw_eth_ofdata_to_platdata()
1392 priv->data.slave_data[slave_index].phy_addr = in cpsw_eth_ofdata_to_platdata()
1393 fdtdec_get_int(gd->fdt_blob, in cpsw_eth_ofdata_to_platdata()
1394 priv->data.slave_data[slave_index].phy_of_handle, in cpsw_eth_ofdata_to_platdata()
1395 "reg", -1); in cpsw_eth_ofdata_to_platdata()
1399 priv->data.slave_data[slave_index].phy_addr = in cpsw_eth_ofdata_to_platdata()
1405 if (!strncmp(name, "cpsw-phy-sel", 12)) { in cpsw_eth_ofdata_to_platdata()
1406 priv->data.gmii_sel = cpsw_get_addr_by_node(fdt, in cpsw_eth_ofdata_to_platdata()
1409 if (priv->data.gmii_sel == FDT_ADDR_T_NONE) { in cpsw_eth_ofdata_to_platdata()
1411 return -ENOENT; in cpsw_eth_ofdata_to_platdata()
1414 if (fdt_get_property(fdt, subnode, "rmii-clock-ext", in cpsw_eth_ofdata_to_platdata()
1416 priv->data.rmii_clock_external = true; in cpsw_eth_ofdata_to_platdata()
1422 return -ENOENT; in cpsw_eth_ofdata_to_platdata()
1427 priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET; in cpsw_eth_ofdata_to_platdata()
1428 priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET; in cpsw_eth_ofdata_to_platdata()
1430 if (priv->data.slaves == 2) { in cpsw_eth_ofdata_to_platdata()
1431 priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET; in cpsw_eth_ofdata_to_platdata()
1432 priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET; in cpsw_eth_ofdata_to_platdata()
1435 ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr); in cpsw_eth_ofdata_to_platdata()
1437 pr_err("cpsw read efuse mac failed\n"); in cpsw_eth_ofdata_to_platdata()
1441 pdata->phy_interface = priv->data.slave_data[active_slave].phy_if; in cpsw_eth_ofdata_to_platdata()
1442 if (pdata->phy_interface == -1) { in cpsw_eth_ofdata_to_platdata()
1444 return -EINVAL; in cpsw_eth_ofdata_to_platdata()
1448 cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface); in cpsw_eth_ofdata_to_platdata()
1455 { .compatible = "ti,cpsw" },
1456 { .compatible = "ti,am335x-cpsw" },