xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/am335x-icev2.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/*
7*4882a593Smuzhiyun * AM335x ICE V2 board
8*4882a593Smuzhiyun * http://www.ti.com/tool/tmdsice3359
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/dts-v1/;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun#include "am33xx.dtsi"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun	model = "TI AM3359 ICE-V2";
17*4882a593Smuzhiyun	compatible = "ti,am3359-icev2", "ti,am33xx";
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	memory@80000000 {
20*4882a593Smuzhiyun		device_type = "memory";
21*4882a593Smuzhiyun		reg = <0x80000000 0x10000000>; /* 256 MB */
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	chosen {
25*4882a593Smuzhiyun		stdout-path = &uart3;
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	vbat: fixedregulator0 {
29*4882a593Smuzhiyun		compatible = "regulator-fixed";
30*4882a593Smuzhiyun		regulator-name = "vbat";
31*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
32*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
33*4882a593Smuzhiyun		regulator-boot-on;
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	vtt_fixed: fixedregulator1 {
37*4882a593Smuzhiyun		compatible = "regulator-fixed";
38*4882a593Smuzhiyun		regulator-name = "vtt";
39*4882a593Smuzhiyun		regulator-min-microvolt = <1500000>;
40*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
41*4882a593Smuzhiyun		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
42*4882a593Smuzhiyun		regulator-always-on;
43*4882a593Smuzhiyun		regulator-boot-on;
44*4882a593Smuzhiyun		enable-active-high;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	leds-iio {
48*4882a593Smuzhiyun		status = "disabled";
49*4882a593Smuzhiyun		compatible = "gpio-leds";
50*4882a593Smuzhiyun		led-out0 {
51*4882a593Smuzhiyun			label = "out0";
52*4882a593Smuzhiyun			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
53*4882a593Smuzhiyun			default-state = "off";
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		led-out1 {
57*4882a593Smuzhiyun			label = "out1";
58*4882a593Smuzhiyun			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
59*4882a593Smuzhiyun			default-state = "off";
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		led-out2 {
63*4882a593Smuzhiyun			label = "out2";
64*4882a593Smuzhiyun			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
65*4882a593Smuzhiyun			default-state = "off";
66*4882a593Smuzhiyun		};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun		led-out3 {
69*4882a593Smuzhiyun			label = "out3";
70*4882a593Smuzhiyun			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
71*4882a593Smuzhiyun			default-state = "off";
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun		led-out4 {
75*4882a593Smuzhiyun			label = "out4";
76*4882a593Smuzhiyun			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
77*4882a593Smuzhiyun			default-state = "off";
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun		led-out5 {
81*4882a593Smuzhiyun			label = "out5";
82*4882a593Smuzhiyun			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
83*4882a593Smuzhiyun			default-state = "off";
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun		led-out6 {
87*4882a593Smuzhiyun			label = "out6";
88*4882a593Smuzhiyun			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
89*4882a593Smuzhiyun			default-state = "off";
90*4882a593Smuzhiyun		};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		led-out7 {
93*4882a593Smuzhiyun			label = "out7";
94*4882a593Smuzhiyun			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
95*4882a593Smuzhiyun			default-state = "off";
96*4882a593Smuzhiyun		};
97*4882a593Smuzhiyun	};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	/* Tricolor status LEDs */
100*4882a593Smuzhiyun	leds1 {
101*4882a593Smuzhiyun		compatible = "gpio-leds";
102*4882a593Smuzhiyun		pinctrl-names = "default";
103*4882a593Smuzhiyun		pinctrl-0 = <&user_leds>;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun		led0 {
106*4882a593Smuzhiyun			label = "status0:red:cpu0";
107*4882a593Smuzhiyun			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
108*4882a593Smuzhiyun			default-state = "off";
109*4882a593Smuzhiyun			linux,default-trigger = "cpu0";
110*4882a593Smuzhiyun		};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun		led1 {
113*4882a593Smuzhiyun			label = "status0:green:usr";
114*4882a593Smuzhiyun			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
115*4882a593Smuzhiyun			default-state = "off";
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun		led2 {
119*4882a593Smuzhiyun			label = "status0:yellow:usr";
120*4882a593Smuzhiyun			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
121*4882a593Smuzhiyun			default-state = "off";
122*4882a593Smuzhiyun		};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		led3 {
125*4882a593Smuzhiyun			label = "status1:red:mmc0";
126*4882a593Smuzhiyun			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
127*4882a593Smuzhiyun			default-state = "off";
128*4882a593Smuzhiyun			linux,default-trigger = "mmc0";
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		led4 {
132*4882a593Smuzhiyun			label = "status1:green:usr";
133*4882a593Smuzhiyun			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
134*4882a593Smuzhiyun			default-state = "off";
135*4882a593Smuzhiyun		};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		led5 {
138*4882a593Smuzhiyun			label = "status1:yellow:usr";
139*4882a593Smuzhiyun			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
140*4882a593Smuzhiyun			default-state = "off";
141*4882a593Smuzhiyun		};
142*4882a593Smuzhiyun	};
143*4882a593Smuzhiyun	gpio-decoder {
144*4882a593Smuzhiyun		compatible = "gpio-decoder";
145*4882a593Smuzhiyun		gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
146*4882a593Smuzhiyun			<&pca9536 2 GPIO_ACTIVE_HIGH>,
147*4882a593Smuzhiyun			<&pca9536 1 GPIO_ACTIVE_HIGH>,
148*4882a593Smuzhiyun			<&pca9536 0 GPIO_ACTIVE_HIGH>;
149*4882a593Smuzhiyun		linux,axis = <0>; /* ABS_X */
150*4882a593Smuzhiyun		decoder-max-value = <9>;
151*4882a593Smuzhiyun	};
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&am33xx_pinmux {
155*4882a593Smuzhiyun	user_leds: user_leds {
156*4882a593Smuzhiyun		pinctrl-single,pins = <
157*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
158*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
159*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
160*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
161*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
162*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
163*4882a593Smuzhiyun		>;
164*4882a593Smuzhiyun	};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun	mmc0_pins_default: mmc0_pins_default {
167*4882a593Smuzhiyun		pinctrl-single,pins = <
168*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
169*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
170*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
171*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
172*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
173*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
174*4882a593Smuzhiyun		>;
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	i2c0_pins_default: i2c0_pins_default {
178*4882a593Smuzhiyun		pinctrl-single,pins = <
179*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
180*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
181*4882a593Smuzhiyun		>;
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	spi0_pins_default: spi0_pins_default {
185*4882a593Smuzhiyun		pinctrl-single,pins = <
186*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
187*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
188*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
189*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
190*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)
191*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
192*4882a593Smuzhiyun		>;
193*4882a593Smuzhiyun	};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	uart3_pins_default: uart3_pins_default {
196*4882a593Smuzhiyun		pinctrl-single,pins = <
197*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
198*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
199*4882a593Smuzhiyun		>;
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	cpsw_default: cpsw_default {
203*4882a593Smuzhiyun		pinctrl-single,pins = <
204*4882a593Smuzhiyun			/* Slave 1, RMII mode */
205*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
206*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
207*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
208*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
209*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
210*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
211*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
212*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_txen.rmii1_txen */
213*4882a593Smuzhiyun			/* Slave 2, RMII mode */
214*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_wait0.rmii2_crs_dv */
215*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_col.rmii2_refclk */
216*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a11.rmii2_rxd0 */
217*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_a10.rmii2_rxd1 */
218*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)	/* gpmc_wpn.rmii2_rxerr */
219*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a5.rmii2_txd0 */
220*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a4.rmii2_txd1 */
221*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* gpmc_a0.rmii2_txen */
222*4882a593Smuzhiyun		>;
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun	cpsw_sleep: cpsw_sleep {
226*4882a593Smuzhiyun		pinctrl-single,pins = <
227*4882a593Smuzhiyun			/* Slave 1 reset value */
228*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
229*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
230*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
231*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
232*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
233*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
234*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
235*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun			/* Slave 2 reset value */
238*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
239*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
240*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
241*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
242*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
243*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
244*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
245*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
246*4882a593Smuzhiyun		>;
247*4882a593Smuzhiyun	};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun	davinci_mdio_default: davinci_mdio_default {
250*4882a593Smuzhiyun		pinctrl-single,pins = <
251*4882a593Smuzhiyun			/* MDIO */
252*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
253*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
254*4882a593Smuzhiyun		>;
255*4882a593Smuzhiyun	};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun	davinci_mdio_sleep: davinci_mdio_sleep {
258*4882a593Smuzhiyun		pinctrl-single,pins = <
259*4882a593Smuzhiyun			/* MDIO reset value */
260*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
261*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
262*4882a593Smuzhiyun		>;
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun&i2c0 {
267*4882a593Smuzhiyun	pinctrl-names = "default";
268*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins_default>;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun	status = "okay";
271*4882a593Smuzhiyun	clock-frequency = <400000>;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun	tps: power-controller@2d {
274*4882a593Smuzhiyun		reg = <0x2d>;
275*4882a593Smuzhiyun	};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun	tpic2810: gpio@60 {
278*4882a593Smuzhiyun		compatible = "ti,tpic2810";
279*4882a593Smuzhiyun		reg = <0x60>;
280*4882a593Smuzhiyun		gpio-controller;
281*4882a593Smuzhiyun		#gpio-cells = <2>;
282*4882a593Smuzhiyun	};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun	pca9536: gpio@41 {
285*4882a593Smuzhiyun		compatible = "ti,pca9536";
286*4882a593Smuzhiyun		reg = <0x41>;
287*4882a593Smuzhiyun		gpio-controller;
288*4882a593Smuzhiyun		#gpio-cells = <2>;
289*4882a593Smuzhiyun	};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun	/* osd9616p0899-10 */
292*4882a593Smuzhiyun	display@3c {
293*4882a593Smuzhiyun		compatible = "solomon,ssd1306fb-i2c";
294*4882a593Smuzhiyun		reg = <0x3c>;
295*4882a593Smuzhiyun		solomon,height = <16>;
296*4882a593Smuzhiyun		solomon,width = <96>;
297*4882a593Smuzhiyun		solomon,com-seq;
298*4882a593Smuzhiyun		solomon,com-invdir;
299*4882a593Smuzhiyun		solomon,page-offset = <0>;
300*4882a593Smuzhiyun		solomon,prechargep1 = <2>;
301*4882a593Smuzhiyun		solomon,prechargep2 = <13>;
302*4882a593Smuzhiyun	};
303*4882a593Smuzhiyun};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun&spi0 {
306*4882a593Smuzhiyun	status = "okay";
307*4882a593Smuzhiyun	pinctrl-names = "default";
308*4882a593Smuzhiyun	pinctrl-0 = <&spi0_pins_default>;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun	sn65hvs882@1 {
311*4882a593Smuzhiyun		compatible = "pisosr-gpio";
312*4882a593Smuzhiyun		gpio-controller;
313*4882a593Smuzhiyun		#gpio-cells = <2>;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun		load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun		reg = <1>;
318*4882a593Smuzhiyun		spi-max-frequency = <1000000>;
319*4882a593Smuzhiyun		spi-cpol;
320*4882a593Smuzhiyun	};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun	spi_nor: flash@0 {
323*4882a593Smuzhiyun		#address-cells = <1>;
324*4882a593Smuzhiyun		#size-cells = <1>;
325*4882a593Smuzhiyun		compatible = "winbond,w25q64", "jedec,spi-nor";
326*4882a593Smuzhiyun		spi-max-frequency = <80000000>;
327*4882a593Smuzhiyun		m25p,fast-read;
328*4882a593Smuzhiyun		reg = <0>;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun		partition@0 {
331*4882a593Smuzhiyun			label = "u-boot-spl";
332*4882a593Smuzhiyun			reg = <0x0 0x80000>;
333*4882a593Smuzhiyun			read-only;
334*4882a593Smuzhiyun		};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun		partition@1 {
337*4882a593Smuzhiyun			label = "u-boot";
338*4882a593Smuzhiyun			reg = <0x80000 0x100000>;
339*4882a593Smuzhiyun			read-only;
340*4882a593Smuzhiyun		};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun		partition@2 {
343*4882a593Smuzhiyun			label = "u-boot-env";
344*4882a593Smuzhiyun			reg = <0x180000 0x20000>;
345*4882a593Smuzhiyun			read-only;
346*4882a593Smuzhiyun		};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun		partition@3 {
349*4882a593Smuzhiyun			label = "misc";
350*4882a593Smuzhiyun			reg = <0x1A0000 0x660000>;
351*4882a593Smuzhiyun		};
352*4882a593Smuzhiyun	};
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&tscadc {
357*4882a593Smuzhiyun	status = "okay";
358*4882a593Smuzhiyun	adc {
359*4882a593Smuzhiyun		ti,adc-channels = <1 2 3 4 5 6 7>;
360*4882a593Smuzhiyun	};
361*4882a593Smuzhiyun};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun#include "tps65910.dtsi"
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun&tps {
366*4882a593Smuzhiyun	vcc1-supply = <&vbat>;
367*4882a593Smuzhiyun	vcc2-supply = <&vbat>;
368*4882a593Smuzhiyun	vcc3-supply = <&vbat>;
369*4882a593Smuzhiyun	vcc4-supply = <&vbat>;
370*4882a593Smuzhiyun	vcc5-supply = <&vbat>;
371*4882a593Smuzhiyun	vcc6-supply = <&vbat>;
372*4882a593Smuzhiyun	vcc7-supply = <&vbat>;
373*4882a593Smuzhiyun	vccio-supply = <&vbat>;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun	regulators {
376*4882a593Smuzhiyun		vrtc_reg: regulator@0 {
377*4882a593Smuzhiyun			regulator-always-on;
378*4882a593Smuzhiyun		};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun		vio_reg: regulator@1 {
381*4882a593Smuzhiyun			regulator-always-on;
382*4882a593Smuzhiyun		};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun		vdd1_reg: regulator@2 {
385*4882a593Smuzhiyun			regulator-name = "vdd_mpu";
386*4882a593Smuzhiyun			regulator-min-microvolt = <912500>;
387*4882a593Smuzhiyun			regulator-max-microvolt = <1326000>;
388*4882a593Smuzhiyun			regulator-boot-on;
389*4882a593Smuzhiyun			regulator-always-on;
390*4882a593Smuzhiyun		};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun		vdd2_reg: regulator@3 {
393*4882a593Smuzhiyun			regulator-name = "vdd_core";
394*4882a593Smuzhiyun			regulator-min-microvolt = <912500>;
395*4882a593Smuzhiyun			regulator-max-microvolt = <1144000>;
396*4882a593Smuzhiyun			regulator-boot-on;
397*4882a593Smuzhiyun			regulator-always-on;
398*4882a593Smuzhiyun		};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun		vdd3_reg: regulator@4 {
401*4882a593Smuzhiyun			regulator-always-on;
402*4882a593Smuzhiyun		};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun		vdig1_reg: regulator@5 {
405*4882a593Smuzhiyun			regulator-always-on;
406*4882a593Smuzhiyun		};
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun		vdig2_reg: regulator@6 {
409*4882a593Smuzhiyun			regulator-always-on;
410*4882a593Smuzhiyun		};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun		vpll_reg: regulator@7 {
413*4882a593Smuzhiyun			regulator-always-on;
414*4882a593Smuzhiyun		};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun		vdac_reg: regulator@8 {
417*4882a593Smuzhiyun			regulator-always-on;
418*4882a593Smuzhiyun		};
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun		vaux1_reg: regulator@9 {
421*4882a593Smuzhiyun			regulator-always-on;
422*4882a593Smuzhiyun		};
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun		vaux2_reg: regulator@10 {
425*4882a593Smuzhiyun			regulator-always-on;
426*4882a593Smuzhiyun		};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun		vaux33_reg: regulator@11 {
429*4882a593Smuzhiyun			regulator-always-on;
430*4882a593Smuzhiyun		};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun		vmmc_reg: regulator@12 {
433*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
434*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
435*4882a593Smuzhiyun			regulator-always-on;
436*4882a593Smuzhiyun		};
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun&mmc1 {
441*4882a593Smuzhiyun	status = "okay";
442*4882a593Smuzhiyun	vmmc-supply = <&vmmc_reg>;
443*4882a593Smuzhiyun	bus-width = <4>;
444*4882a593Smuzhiyun	pinctrl-names = "default";
445*4882a593Smuzhiyun	pinctrl-0 = <&mmc0_pins_default>;
446*4882a593Smuzhiyun};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun&gpio0_target {
449*4882a593Smuzhiyun	/* Do not idle the GPIO used for holding the VTT regulator */
450*4882a593Smuzhiyun	ti,no-reset-on-init;
451*4882a593Smuzhiyun	ti,no-idle-on-init;
452*4882a593Smuzhiyun};
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun&uart3 {
455*4882a593Smuzhiyun	pinctrl-names = "default";
456*4882a593Smuzhiyun	pinctrl-0 = <&uart3_pins_default>;
457*4882a593Smuzhiyun	status = "okay";
458*4882a593Smuzhiyun};
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun&gpio3 {
461*4882a593Smuzhiyun	p4 {
462*4882a593Smuzhiyun		gpio-hog;
463*4882a593Smuzhiyun		gpios = <4 GPIO_ACTIVE_HIGH>;
464*4882a593Smuzhiyun		output-high;
465*4882a593Smuzhiyun		line-name = "PR1_MII_CTRL";
466*4882a593Smuzhiyun	};
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun	p10 {
469*4882a593Smuzhiyun		gpio-hog;
470*4882a593Smuzhiyun		gpios = <10 GPIO_ACTIVE_HIGH>;
471*4882a593Smuzhiyun		/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
472*4882a593Smuzhiyun		output-high;
473*4882a593Smuzhiyun		line-name = "MUX_MII_CTL1";
474*4882a593Smuzhiyun	};
475*4882a593Smuzhiyun};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun&cpsw_emac0 {
478*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
479*4882a593Smuzhiyun	phy-mode = "rmii";
480*4882a593Smuzhiyun	dual_emac_res_vlan = <1>;
481*4882a593Smuzhiyun};
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun&cpsw_emac1 {
484*4882a593Smuzhiyun	phy-handle = <&ethphy1>;
485*4882a593Smuzhiyun	phy-mode = "rmii";
486*4882a593Smuzhiyun	dual_emac_res_vlan = <2>;
487*4882a593Smuzhiyun};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun&mac {
490*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
491*4882a593Smuzhiyun	pinctrl-0 = <&cpsw_default>;
492*4882a593Smuzhiyun	pinctrl-1 = <&cpsw_sleep>;
493*4882a593Smuzhiyun	status = "okay";
494*4882a593Smuzhiyun	dual_emac;
495*4882a593Smuzhiyun};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun&davinci_mdio {
498*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
499*4882a593Smuzhiyun	pinctrl-0 = <&davinci_mdio_default>;
500*4882a593Smuzhiyun	pinctrl-1 = <&davinci_mdio_sleep>;
501*4882a593Smuzhiyun	status = "okay";
502*4882a593Smuzhiyun	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
503*4882a593Smuzhiyun	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun	ethphy0: ethernet-phy@1 {
506*4882a593Smuzhiyun		reg = <1>;
507*4882a593Smuzhiyun	};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun	ethphy1: ethernet-phy@3 {
510*4882a593Smuzhiyun		reg = <3>;
511*4882a593Smuzhiyun	};
512*4882a593Smuzhiyun};
513