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/optee_os/
H A DMAINTAINERS43 F: core/arch/arm/plat-vexpress/
48 F: core/arch/arm/plat-vexpress/
53 F: core/arch/arm/plat-corstone1000/
58 F: core/arch/plat-automotive_rd
63 F: core/arch/arm/plat-sunxi/
68 F: core/arch/arm/plat-sunxi/
74 F: core/arch/arm/plat-versal2/
75 F: core/drivers/amd/
80 F: core/arch/arm/plat-amlogic/
85 F: core/arch/arm/plat-sam/
[all …]
/optee_os/core/drivers/clk/sam/
H A Dclk-sam9x60-pll.c49 struct sam9x60_pll_core core; member
55 struct sam9x60_pll_core core; member
97 struct sam9x60_pll_core *core = &frac->core; in sam9x60_frac_pll_set() local
98 vaddr_t regmap = frac->core.base; in sam9x60_frac_pll_set()
104 AT91_PMC_PLL_UPDT_ID_MASK, core->id); in sam9x60_frac_pll_set()
106 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; in sam9x60_frac_pll_set()
107 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; in sam9x60_frac_pll_set()
109 if (sam9x60_frac_pll_ready(regmap, core->id) && in sam9x60_frac_pll_set()
114 if (core->charac->upll) in sam9x60_frac_pll_set()
121 SHIFT_U32(frac->mul, core->layout->mul_shift) | in sam9x60_frac_pll_set()
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/optee_os/core/drivers/pm/imx/
H A Dlocal.h9 * Read the SRC GPR ARG register for the given core number
10 * @cpu Core number
15 * Set the SRC GPR ARG register for the given core number
16 * @cpu Core number
22 * Read the SRC GPR ENTRY register for the given core number
23 * @cpu Core number
28 * Set the SRC GPR ENTRY register for the given core number
29 * @cpu Core number
35 * Release the given core
36 * @cpu Core number
[all …]
/optee_os/core/
H A Dcore.mk4 sm := core
7 arch-dir := core/arch/$(ARCH)
11 # $(ARCH).mk also sets the compiler for the core module
12 include core/arch/$(ARCH)/$(ARCH).mk
15 ifeq ($(arch-bits-core),64)
30 include core/crypto.mk
33 include core/lib/scmi-server/conf.mk
40 cppflags$(sm) += -I$(out-dir)/core/include
41 cppflags$(sm) += $(core-platform-cppflags)
42 cflags$(sm) += $(core-platform-cflags)
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H A Dcrypto.mk13 CRYPTO_MAKEFILES := $(sort $(wildcard core/drivers/crypto/*/crypto.mk))
82 # Define the maximum size, in bits, for big numbers in the TEE core (privileged
85 # implemented by the TEE core.
205 core-ltc-vars = AES DES
206 core-ltc-vars += ECB CBC CTR CTS XTS
207 core-ltc-vars += MD5 SHA1 SHA224 SHA256 SHA384 SHA512 SHA512_256
208 core-ltc-vars += SHA3_224 SHA3_256 SHA3_384 SHA3_512 SHAKE128 SHAKE256
209 core-ltc-vars += HMAC CMAC CBC_MAC
210 core-ltc-vars += CCM
212 core-ltc-vars += GCM
[all …]
H A Dsub.mk54 core-embed-fdt-dts = $(arch-dir)/dts/$(CFG_EMBED_DTB_SOURCE_FILE)
55 core-embed-fdt-dtb = $(out-dir)/$(arch-dir)/dts/$(CFG_EMBED_DTB_SOURCE_FILE:.dts=.dtb)
56 core-embed-fdt-c = $(out-dir)/$(arch-dir)/dts/$(CFG_EMBED_DTB_SOURCE_FILE:.dts=.c)
59 depends-embedded_secure_dtb = $(core-embed-fdt-dtb) scripts/bin_to_c.py
61 --bin $(core-embed-fdt-dtb) \
63 --out $(core-embed-fdt-c)
64 $(eval $(call gen-dtb-file,$(core-embed-fdt-dts),$(core-embed-fdt-dtb)))
/optee_os/core/arch/arm/plat-rockchip/
H A Dgrf.h12 #define CORE_WFE_MASK(core) SHIFT_U32(0x02, (core)) argument
13 #define CORE_WFI_MASK(core) SHIFT_U32(0x20, (core)) argument
14 #define CORE_WFE_I_MASK(core) (CORE_WFI_MASK(core) | CORE_WFE_MASK(core)) argument
H A Dcru.h31 #define CORE_SOFT_RESET(core) SHIFT_U32(0x100010, (core)) argument
32 #define CORE_SOFT_RELEASE(core) SHIFT_U32(0x100000, (core)) argument
33 #define CORE_HELD_IN_RESET(core) SHIFT_U32(0x000010, (core)) argument
H A Dpsci_rk322x.c135 /* core */ in plls_power_down()
188 /* core */ in plls_restore()
203 static bool wait_core_wfe_i(uint32_t core) in wait_core_wfe_i() argument
208 wfei_mask = CORE_WFE_I_MASK(core); in wait_core_wfe_i()
218 static bool core_held_in_reset(uint32_t core) in core_held_in_reset() argument
225 return val & CORE_HELD_IN_RESET(core); in core_held_in_reset()
274 /* soft reset core */ in psci_cpu_on()
280 /* soft release core */ in psci_cpu_on()
304 uint32_t core = get_core_pos(); in psci_cpu_off() local
306 if ((core == 0) || (core >= CFG_TEE_CORE_NB_CORE)) in psci_cpu_off()
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H A Dconf.mk12 include ./core/arch/arm/cpu/cortex-a7.mk
30 include core/arch/arm/cpu/cortex-armv8-0.mk
48 include core/arch/arm/cpu/cortex-armv8-0.mk
60 include core/arch/arm/cpu/cortex-armv8-0.mk
/optee_os/core/arch/riscv/
H A Driscv.mk1 # Setup compiler for the core module
3 arch-bits-core := 64
5 arch-bits-core := 32
7 CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core))
12 # Defines the cc-option macro using the compiler set for the core module
40 # CFG_WITH_LPAE is ARM-related flag, however, it is used by core code.
109 core-platform-cppflags += -I$(arch-dir)/include
110 core-platform-subdirs += \
161 core-platform-cflags += $(platform-cflags-optimization)
162 core-platform-cflags += $(platform-cflags-generic)
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/optee_os/core/arch/arm/
H A Darm.mk1 # Setup compiler for the core module
3 arch-bits-core := 64
5 arch-bits-core := 32
7 CROSS_COMPILE_core := $(CROSS_COMPILE$(arch-bits-core))
11 # Defines the cc-option macro using the compiler set for the core module
88 # Adds workarounds against if ARM core is configured with Non-maskable FIQ
107 # SPMC configuration "S-EL1 SPMC" where SPM Core is implemented at S-EL1,
114 # SPMC configuration "S-EL2 SPMC" where SPM Core is implemented at S-EL2,
125 # SPMC configuration "EL3 SPMC" where SPM Core is implemented at EL3, that
212 core-platform-cppflags += -I$(arch-dir)/include
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/optee_os/scripts/
H A Dcheckpatch_inc.sh7 core/include/gen-asm-defines.h \
8 core/lib/lib{fdt,tomcrypt} core/lib/zlib \
12 core/arch/arm/include/arm{32,64}.h \
13 core/arch/arm/plat-ti/api_monitor_index_a{9,15}.h \
14 core/arch/arm/dts \
16 core/lib/qcbor \
17 core/arch/riscv/include/encoding.h )
/optee_os/ldelf/
H A Dldelf.mk9 cppflags$(sm) := $(core-platform-cppflags)
10 cflags$(sm) := $(core-platform-cflags) -fpie -fvisibility=hidden
11 aflags$(sm) := $(core-platform-aflags)
13 # ldelf is compiled for the same arch or register width as core
26 arch-bits-$(sm) := $(arch-bits-core)
36 # Use same compiler as for core
/optee_os/core/arch/arm/plat-ls/
H A Dconf.mk17 include core/arch/arm/cpu/cortex-armv8-0.mk
26 include core/arch/arm/cpu/cortex-armv8-0.mk
34 include core/arch/arm/cpu/cortex-armv8-0.mk
42 include core/arch/arm/cpu/cortex-armv8-0.mk
51 include core/arch/arm/cpu/cortex-armv8-0.mk
60 include core/arch/arm/cpu/cortex-armv8-0.mk
78 include core/arch/arm/cpu/cortex-armv8-0.mk
96 include core/arch/arm/cpu/cortex-armv8-0.mk
/optee_os/mk/
H A Dconfig.mk1 # Default configuration values for OP-TEE core (all platforms).
3 # Platform-specific overrides are in core/arch/arm32/plat-*/conf.mk.
12 # 4. The platform-specific configuration file: core/arch/arm32/plat-*/conf.mk
62 # Enabling CFG_DEBUG_INFO makes debug information embedded in core.
65 # If y, enable debug features of the TEE core (assertions and lock checks
71 # Log levels for the TEE core. Defines which core messages are displayed
72 # on the secure console. Disabling core log (level set to 0) also disables
100 # - To debug TEE core allocations: build OP-TEE with:
109 # (severity, core ID, thread ID, component name, function name, line number)
277 # Stack unwinding: print a stack dump to the console on core or TA abort, or
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/optee_os/core/arch/arm/plat-marvell/
H A Dconf.mk4 include core/arch/arm/cpu/cortex-armv8-0.mk
18 include core/arch/arm/cpu/cortex-armv8-0.mk
33 include core/arch/arm/cpu/cortex-armv8-0.mk
52 include core/arch/arm/cpu/cortex-armv8-0.mk
71 include core/arch/arm/cpu/cortex-armv8-0.mk
90 include core/arch/arm/cpu/cortex-armv8-0.mk
107 include core/arch/arm/cpu/cortex-armv8-0.mk
124 include core/arch/arm/cpu/cortex-armv8-0.mk
141 include core/arch/arm/cpu/cortex-armv8-0.mk
158 include core/arch/arm/cpu/cortex-armv8-0.mk
[all …]
/optee_os/lib/libmbedtls/mbedtls/library/
H A Dpsa_crypto_aead.h147 * mbedtls_psa_aead_encrypt_setup(), the operation is reset by the PSA core by a
148 * call to mbedtls_psa_aead_abort(). The PSA core may call
190 * mbedtls_psa_aead_decrypt_setup(), the PSA core resets the operation by a
191 * call to mbedtls_psa_aead_abort(). The PSA core may call
235 * The PSA core calls mbedtls_psa_aead_encrypt_setup() or
238 * If this function returns an error status, the PSA core will call
265 * The PSA core calls this function before calling mbedtls_psa_aead_update_ad()
270 * The PSA core may call this function before or after setting the nonce with
277 * If this function returns an error status, the PSA core calls
308 * The PSA core can call this function multiple times to pass successive
[all …]
H A Dpsa_crypto_mac.h134 * The PSA core calls mbedtls_psa_mac_sign_setup() or
137 * If this function returns an error status, the PSA core aborts the
164 * The PSA core calls mbedtls_psa_mac_sign_setup() before calling this function.
168 * Whether this function returns successfully or not, the PSA core subsequently
174 * core guarantees this is a valid MAC length for the
208 * The PSA core calls mbedtls_psa_mac_verify_setup() before calling this
214 * Whether this function returns successfully or not, the PSA core subsequently
220 * core guarantees that this length is a valid MAC
247 * The PSA core may call this function any time after the operation object has
/optee_os/core/lib/libefi/include/efi/
H A Dmpinfo.h50 uint32_t core; member
62 uint32_t core; member
73 * the physical core number within package, and
74 * logical thread number within core.
110 * the physical core number within package, and logical thread number
111 * within core.
/optee_os/core/arch/arm/plat-rcar/
H A Dcore_pos_a64.S28 * as follows AFF2 -> cluster, AFF1 -> core, AFF0 -> thread
40 * The code below normalizes the M3W/M3W+ core enumeration such
41 * that cluster 0 returns core IDs {0, 1} and cluster 1 returns
42 * core IDs {2, 3, 4, 5}. This is achieved by calculating the
43 * core ID as CorePos = CoreId + (ClusterId << (IsM3W ? 1 : 0))
/optee_os/core/arch/arm/plat-ti/
H A Dconf.mk7 include core/arch/arm/cpu/cortex-a15.mk
14 include core/arch/arm/cpu/cortex-a15.mk
21 include core/arch/arm/cpu/cortex-a9.mk
/optee_os/core/arch/arm/plat-d06/
H A Dcore_pos_a64.S14 * bit8~bit10: core index
17 * 96 cores: index = sccl * 24 + ccl * 4 + core
18 * 128 cores: index = sccl * 32 + ccl * 4 + core (now used)
/optee_os/core/arch/arm/plat-stm32mp1/pm/
H A Dpsci.c60 DMSG("core %zu, state %u", pos, core_state[pos]); in psci_affinity_info()
137 /* Need to send SIG#0 over Group0 after individual core 1 reset */ in release_secondary_early_hpen()
160 DMSG("core %zu, ns_entry 0x%" PRIx32 ", state %u", in psci_cpu_on()
200 EMSG("PSCI_CPU_OFF not supported for core #0"); in psci_cpu_off()
204 DMSG("core %u", pos); in psci_cpu_off()
226 DMSG("core %u", get_core_pos()); in psci_system_off()
/optee_os/core/arch/arm/plat-vexpress/
H A Dconf.mk4 include core/arch/arm/cpu/cortex-a15.mk
7 include core/arch/arm/cpu/cortex-armv8-0.mk
11 include core/arch/arm/cpu/cortex-armv8-0.mk
24 include core/arch/arm/cpu/cortex-armv8-0.mk
29 include core/arch/arm/cpu/cortex-armv8-0.mk
126 # core/arch/arm/kernel/generic_boot.c to check that we got it right

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