drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69

drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set

drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set correct ID
to PMC_PLL_UPDT to avoid operating on wrong PMC_PLL_CTRLx.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: extend the time for waiting PLL ready

The start-up time (simulation data) of sama7g5 PLL is 50us in condition
reaching 95% of target frequency. The PLL lock status bit is not set

drivers: clk: sam: extend the time for waiting PLL ready

The start-up time (simulation data) of sama7g5 PLL is 50us in condition
reaching 95% of target frequency. The PLL lock status bit is not set a few
times with current timeout setting. Extend the time to make sure the check
is successful for any cases.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add PLL clock driver for sama7g5

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for
configuring sama7g5 PLL.

Signed-off-by: Tony Han <tony.han@microchip.

drivers: clk: sam: add PLL clock driver for sama7g5

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for
configuring sama7g5 PLL.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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