1a7bd58f7SSahil MalhotraPLATFORM_FLAVOR ?= ls1012ardb 285278139SSumit Garg 3dffb0049SJerome Forissier$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4cd629100Syanyan-wrs$(call force,CFG_GIC,y) 5dffb0049SJerome Forissier$(call force,CFG_16550_UART,y) 6f6c354e2SPriyanka Singh$(call force,CFG_LS,y) 7dffb0049SJerome Forissier 8929b5671SVinitha V Pillai$(call force,CFG_DRAM0_BASE,0x80000000) 9929b5671SVinitha V Pillai$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10929b5671SVinitha V Pillai 11f55f232cSClement FaureCFG_ENABLE_EMBEDDED_TESTS ?= y 12ab68656bSClement FaureCFG_PKCS11_TA ?= y 13f55f232cSClement Faure 14768500edSFranck LENORMANDCFG_CORE_HEAP_SIZE ?= 131072 15768500edSFranck LENORMAND 162863328cSPankaj Guptaifeq ($(PLATFORM_FLAVOR),ls1012ardb) 172863328cSPankaj Guptainclude core/arch/arm/cpu/cortex-armv8-0.mk 189460285eSJerome Forissier$(call force,CFG_TEE_CORE_NB_CORE,1) 19929b5671SVinitha V Pillai$(call force,CFG_DRAM0_SIZE,0x40000000) 20929b5671SVinitha V Pillai$(call force,CFG_CORE_CLUSTER_SHIFT,2) 2169ecfb92SSahil MalhotraCFG_NUM_THREADS ?= 2 22700b428dSEtienne CarriereCFG_SHMEM_SIZE ?= 0x00200000 232863328cSPankaj Guptaendif 242863328cSPankaj Gupta 252b9f2392SSumit Gargifeq ($(PLATFORM_FLAVOR),ls1043ardb) 262b9f2392SSumit Garginclude core/arch/arm/cpu/cortex-armv8-0.mk 279460285eSJerome Forissier$(call force,CFG_TEE_CORE_NB_CORE,4) 28929b5671SVinitha V Pillai$(call force,CFG_DRAM0_SIZE,0x80000000) 29929b5671SVinitha V Pillai$(call force,CFG_CORE_CLUSTER_SHIFT,2) 30700b428dSEtienne CarriereCFG_SHMEM_SIZE ?= 0x00200000 312b9f2392SSumit Gargendif 322b9f2392SSumit Garg 332b9f2392SSumit Gargifeq ($(PLATFORM_FLAVOR),ls1046ardb) 342b9f2392SSumit Garginclude core/arch/arm/cpu/cortex-armv8-0.mk 359460285eSJerome Forissier$(call force,CFG_TEE_CORE_NB_CORE,4) 36929b5671SVinitha V Pillai$(call force,CFG_DRAM0_SIZE,0x80000000) 37929b5671SVinitha V Pillai$(call force,CFG_CORE_CLUSTER_SHIFT,2) 38700b428dSEtienne CarriereCFG_SHMEM_SIZE ?= 0x00200000 392b9f2392SSumit Gargendif 402b9f2392SSumit Garg 410ecda02bSVinitha V Pillaiifeq ($(PLATFORM_FLAVOR),ls1088ardb) 420ecda02bSVinitha V Pillaiinclude core/arch/arm/cpu/cortex-armv8-0.mk 430ecda02bSVinitha V Pillai$(call force,CFG_TEE_CORE_NB_CORE,8) 440ecda02bSVinitha V Pillai$(call force,CFG_DRAM0_SIZE,0x80000000) 450ecda02bSVinitha V Pillai$(call force,CFG_CORE_CLUSTER_SHIFT,2) 460ecda02bSVinitha V Pillai$(call force,CFG_ARM_GICV3,y) 470ecda02bSVinitha V PillaiCFG_SHMEM_SIZE ?= 0x00200000 480ecda02bSVinitha V Pillaiendif 490ecda02bSVinitha V Pillai 50a06857f9SVinitha V Pillaiifeq ($(PLATFORM_FLAVOR),ls2088ardb) 51a06857f9SVinitha V Pillaiinclude core/arch/arm/cpu/cortex-armv8-0.mk 52a06857f9SVinitha V Pillai$(call force,CFG_TEE_CORE_NB_CORE,8) 53a06857f9SVinitha V Pillai$(call force,CFG_DRAM0_SIZE,0x80000000) 54a06857f9SVinitha V Pillai$(call force,CFG_CORE_CLUSTER_SHIFT,1) 55a06857f9SVinitha V Pillai$(call force,CFG_ARM_GICV3,y) 56a06857f9SVinitha V PillaiCFG_SHMEM_SIZE ?= 0x00200000 57a06857f9SVinitha V Pillaiendif 58a06857f9SVinitha V Pillai 591a121401SManish Tomarifeq ($(PLATFORM_FLAVOR),lx2160aqds) 601a121401SManish Tomarinclude core/arch/arm/cpu/cortex-armv8-0.mk 611a121401SManish Tomar$(call force,CFG_TEE_CORE_NB_CORE,16) 621a121401SManish Tomar$(call force,CFG_DRAM0_SIZE,0x80000000) 631a121401SManish Tomar$(call force,CFG_DRAM1_BASE,0x2080000000) 641a121401SManish Tomar$(call force,CFG_DRAM1_SIZE,0x1F80000000) 651a121401SManish Tomar$(call force,CFG_CORE_CLUSTER_SHIFT,1) 661a121401SManish Tomar$(call force,CFG_ARM_GICV3,y) 671a121401SManish Tomar$(call force,CFG_PL011,y) 68*bbc33e2aSSahil Malhotra$(call force,CFG_CORE_ARM64_PA_BITS,40) 69fdec073aSSahil Malhotra$(call force,CFG_EMBED_DTB,y) 701c2924e5SSahil Malhotra$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 71819d0141SSahil MalhotraCFG_LS_I2C ?= y 7216c13b4dSManish TomarCFG_LS_GPIO ?= y 733513f269SManish TomarCFG_LS_DSPI ?= y 741a121401SManish TomarCFG_SHMEM_SIZE ?= 0x00200000 751a121401SManish Tomarendif 761a121401SManish Tomar 7773094386SPankaj Guptaifeq ($(PLATFORM_FLAVOR),lx2160ardb) 7873094386SPankaj Guptainclude core/arch/arm/cpu/cortex-armv8-0.mk 7973094386SPankaj Gupta$(call force,CFG_TEE_CORE_NB_CORE,16) 8073094386SPankaj Gupta$(call force,CFG_DRAM0_SIZE,0x80000000) 81a8a14b78SRuchika Gupta$(call force,CFG_DRAM1_BASE,0x2080000000) 82a8a14b78SRuchika Gupta$(call force,CFG_DRAM1_SIZE,0x1F80000000) 8373094386SPankaj Gupta$(call force,CFG_CORE_CLUSTER_SHIFT,1) 8473094386SPankaj Gupta$(call force,CFG_ARM_GICV3,y) 8573094386SPankaj Gupta$(call force,CFG_PL011,y) 86*bbc33e2aSSahil Malhotra$(call force,CFG_CORE_ARM64_PA_BITS,40) 87fdec073aSSahil Malhotra$(call force,CFG_EMBED_DTB,y) 88a10b1b23SSahil Malhotra$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 89819d0141SSahil MalhotraCFG_LS_I2C ?= y 9016c13b4dSManish TomarCFG_LS_GPIO ?= y 913513f269SManish TomarCFG_LS_DSPI ?= y 9273094386SPankaj GuptaCFG_SHMEM_SIZE ?= 0x00200000 9373094386SPankaj Guptaendif 9473094386SPankaj Gupta 955006adaeSSahil Malhotraifeq ($(PLATFORM_FLAVOR),ls1028ardb) 965006adaeSSahil Malhotrainclude core/arch/arm/cpu/cortex-armv8-0.mk 975006adaeSSahil Malhotra$(call force,CFG_TEE_CORE_NB_CORE,2) 985006adaeSSahil Malhotra$(call force,CFG_DRAM0_SIZE,0x80000000) 995006adaeSSahil Malhotra$(call force,CFG_CORE_CLUSTER_SHIFT,1) 1005006adaeSSahil Malhotra$(call force,CFG_ARM_GICV3,y) 1015006adaeSSahil MalhotraCFG_SHMEM_SIZE ?= 0x00200000 1025006adaeSSahil Malhotraendif 1035006adaeSSahil Malhotra 1042b9f2392SSumit Gargifeq ($(platform-flavor-armv8),1) 1052b9f2392SSumit Garg$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 106929b5671SVinitha V PillaiCFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 107929b5671SVinitha V PillaiCFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 108929b5671SVinitha V Pillai#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 109929b5671SVinitha V PillaiCFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 110929b5671SVinitha V Pillai$(call force,CFG_ARM64_core,y) 1118e897b6bSPankaj GuptaCFG_USER_TA_TARGETS ?= ta_arm64 112929b5671SVinitha V Pillaielse 113929b5671SVinitha V Pillai#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 114929b5671SVinitha V PillaiCFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 115929b5671SVinitha V PillaiCFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 116929b5671SVinitha V Pillai#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 117929b5671SVinitha V PillaiCFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 1182b9f2392SSumit Gargendif 1192b9f2392SSumit Garg 120929b5671SVinitha V Pillai#Keeping Number of TEE thread equal to number of cores on the SoC 121c1f648c0SSahil MalhotraCFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE) 1222b9f2392SSumit Garg 123aeb2ac09SJerome Forissierifneq ($(CFG_ARM64_core),y) 124d388d455SJordan Rhee$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 1252b9f2392SSumit Gargendif 1262b9f2392SSumit Garg 12749a4b3bbSPascal BrandCFG_CRYPTO_SIZE_OPTIMIZATION ?= n 128f6c354e2SPriyanka Singh 129f6c354e2SPriyanka Singh# NXP CAAM support is not enabled by default and can be enabled 130f6c354e2SPriyanka Singh# on the command line 131f6c354e2SPriyanka SinghCFG_NXP_CAAM ?= n 132