History log of /optee_os/core/arch/arm/plat-rockchip/psci_rk322x.c (Results 1 – 14 of 14)
Revision Date Author Comments
# c2e4eb43 23-May-2021 Anton Rybakov <a.rybakov@omp.ru>

core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because

core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because physical
address can be mapped in the same time in different virtual
regions with different length. So the first found region
which contains the requested physical address possibly
doesn`t have enough mapped data. This is fixed by adding
the length parameter to phys_to_virt() function. Length
parameter can be set to 1 if caller knows that requested
(pa + len) doesn`t cross mapping granule boundary.

core_mmu_get_va() and io_pa_or_va() functions now are
take length parameter too as they based on phys_to_virt()
in case of MMU enabled.

Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)

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# 65401337 07-Jun-2020 Jens Wiklander <jens.wiklander@linaro.org>

core: remove generic_ from generic_boot

Now that the CFG_GENERIC_BOOT configuration flag has been removed also
remove "generic_" prefix from and in the related files.

Acked-by: Etienne Carriere <et

core: remove generic_ from generic_boot

Now that the CFG_GENERIC_BOOT configuration flag has been removed also
remove "generic_" prefix from and in the related files.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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# a557db0a 09-Oct-2019 Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

plat-rockchip: map io peripherals individually

Most Rockchip platforms will generally only need a very minimal subset
of a SoCs peripherals, so there is no need to map the whole io area
and instead

plat-rockchip: map io peripherals individually

Most Rockchip platforms will generally only need a very minimal subset
of a SoCs peripherals, so there is no need to map the whole io area
and instead we should only map the relevant devices.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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# 890d6751 09-Oct-2019 Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

plat-rockchip: remove boilerplate license blocks

All Rockchip platform files do have SPDX tags denoting the files licenses,
so there is no need to keep the now duplicate license boilerplate around.

plat-rockchip: remove boilerplate license blocks

All Rockchip platform files do have SPDX tags denoting the files licenses,
so there is no need to keep the now duplicate license boilerplate around.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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# 22e7ddf8 12-Feb-2019 Etienne Carriere <etienne.carriere@linaro.org>

rockchip: upgrade from write32() to io_write32() and friends

Replace use of readX() and writeX() with io_readX() and io_writeX().
The former are about to be deprecated in favor to the later.

Signed

rockchip: upgrade from write32() to io_write32() and friends

Replace use of readX() and writeX() with io_readX() and io_writeX().
The former are about to be deprecated in favor to the later.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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# f6bbec8e 24-Apr-2018 Etienne Carriere <etienne.carriere@linaro.org>

core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to ov

core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this
change preserve these configurations.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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# 9a6def2f 05-Mar-2018 Jordan Rhee <jordanrh@microsoft.com>

core: insert memory barrier after write to ns entry context

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordan

core: insert memory barrier after write to ns entry context

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>

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# fb9489aa 17-Oct-2017 Jordan Rhee <jordanrh@microsoft.com>

core: fix psci_cpu_on() to use context_id parameter

The PSCI specification requires the context_id parameter to be
passed in r0 when the core jumps to normal world. Some OS's require
this parameter.

core: fix psci_cpu_on() to use context_id parameter

The PSCI specification requires the context_id parameter to be
passed in r0 when the core jumps to normal world. Some OS's require
this parameter.

Tested on IMX6Quad and IMX7Dual.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>

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# 1bb92983 15-Dec-2017 Jerome Forissier <jerome.forissier@linaro.org>

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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# 789e38a6 06-Nov-2017 Zeng Tao <prime.zeng@hisilicon.com>

core: arm: psci: pass nsec ctx to system_suspend

In the commit 732fc43(core: arm: psci: pass nsec ctx to psci), we have
done the job, but we forgot to follow it in the later commit 1d40eb8
(core: ar

core: arm: psci: pass nsec ctx to system_suspend

In the commit 732fc43(core: arm: psci: pass nsec ctx to psci), we have
done the job, but we forgot to follow it in the later commit 1d40eb8
(core: arm: sm: add PSCI system suspend), fix it in this patch.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

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# 110da4bc 26-Jul-2017 Joseph Chen <chenjh@rock-chips.com>

plat-rockchip: rk322x: add PSCI system suspend

Support gating clks and power down PLLs.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
A

plat-rockchip: rk322x: add PSCI system suspend

Support gating clks and power down PLLs.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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# 1032b987 26-Jul-2017 Joseph Chen <chenjh@rock-chips.com>

plat-rockchip: rk322x: add PSCI features

Add currently implemented PSCI functions.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-

plat-rockchip: rk322x: add PSCI features

Add currently implemented PSCI functions.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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# f1ecb128 26-Jul-2017 Joseph Chen <chenjh@rock-chips.com>

plat-rockchip: rk322x: add PSCI version

Improve PSCI version to PSCI_VERSION_1_0.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-b

plat-rockchip: rk322x: add PSCI version

Improve PSCI version to PSCI_VERSION_1_0.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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# 7176a0b4 21-Jul-2017 Joseph Chen <chenjh@rock-chips.com>

Add plat-rockchip support

Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores

Add plat-rockchip support

Initial version support for rockchip SoCs.(RK322X and next SoCs).

This patch adds to support the RK322X. It is one of the Rockchip
family SoCs, which is a 4*A7 multi-cores ARM SoCs.

plat-rockchip support features:
1.Support SMP cpu boot up and power down;
2.Support system reset;
3.Support GIC driver initialization.

make PLATFORM=rockchip-rk322x

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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