49 	struct sam9x60_pll_core core;  member
55 	struct sam9x60_pll_core core;  member
97 	struct sam9x60_pll_core *core = &frac->core;  in sam9x60_frac_pll_set()  local
98 	vaddr_t regmap = frac->core.base;  in sam9x60_frac_pll_set()
104 			AT91_PMC_PLL_UPDT_ID_MASK, core->id);  in sam9x60_frac_pll_set()
106 	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;  in sam9x60_frac_pll_set()
107 	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;  in sam9x60_frac_pll_set()
109 	if (sam9x60_frac_pll_ready(regmap, core->id) &&  in sam9x60_frac_pll_set()
114 	if (core->charac->upll)  in sam9x60_frac_pll_set()
121 		   SHIFT_U32(frac->mul, core->layout->mul_shift) |  in sam9x60_frac_pll_set()
122 		   SHIFT_U32(frac->frac, core->layout->frac_shift));  in sam9x60_frac_pll_set()
124 	if (core->charac->upll) {  in sam9x60_frac_pll_set()
140 			AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set()
147 			AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set()
149 	if (WAIT_PLL_READY_TIMEOUT(regmap, core->id)) {  in sam9x60_frac_pll_set()
168 	io_clrsetbits32(frac->core.base + AT91_PMC_PLL_UPDT,  in sam9x60_frac_pll_unprepare()
169 			AT91_PMC_PLL_UPDT_ID_MASK, frac->core.id);  in sam9x60_frac_pll_unprepare()
171 	io_clrbits32(frac->core.base + AT91_PMC_PLL_CTRL0,  in sam9x60_frac_pll_unprepare()
174 	if (frac->core.charac->upll)  in sam9x60_frac_pll_unprepare()
175 		io_clrbits32(frac->core.base + AT91_PMC_PLL_ACR,  in sam9x60_frac_pll_unprepare()
179 	io_clrsetbits32(frac->core.base + AT91_PMC_PLL_UPDT,  in sam9x60_frac_pll_unprepare()
181 			AT91_PMC_PLL_UPDT_UPDATE | frac->core.id);  in sam9x60_frac_pll_unprepare()
194 	if (rate < frac->core.charac->output[0].min ||  in sam9x60_frac_pll_compute_mul_frac()
195 	    rate > frac->core.charac->output[0].max)  in sam9x60_frac_pll_compute_mul_frac()
215 	if (tmprate < frac->core.charac->output[0].min ||  in sam9x60_frac_pll_compute_mul_frac()
216 	    tmprate > frac->core.charac->output[0].max)  in sam9x60_frac_pll_compute_mul_frac()
233 	struct sam9x60_pll_core *core = &frac->core;  in sam9x60_frac_pll_set_rate_chg()  local
234 	vaddr_t regmap = core->base;  in sam9x60_frac_pll_set_rate_chg()
239 				AT91_PMC_PLL_UPDT_ID_MASK, core->id);  in sam9x60_frac_pll_set_rate_chg()
242 			   SHIFT_U32(frac->mul, core->layout->mul_shift) |  in sam9x60_frac_pll_set_rate_chg()
243 			   SHIFT_U32(frac->frac, core->layout->frac_shift));  in sam9x60_frac_pll_set_rate_chg()
248 				AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set_rate_chg()
257 				AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_frac_pll_set_rate_chg()
259 		if (WAIT_PLL_READY_TIMEOUT(regmap, core->id)) {  in sam9x60_frac_pll_set_rate_chg()
275 static TEE_Result sam9x60_div_pll_set_div(struct sam9x60_pll_core *core,  in sam9x60_div_pll_set_div()  argument
279 	vaddr_t regmap = core->base;  in sam9x60_div_pll_set_div()
280 	uint32_t enable_mask = enable ? core->layout->endiv_mask : 0;  in sam9x60_div_pll_set_div()
281 	uint32_t ena_val = enable ? BIT(core->layout->endiv_shift) : 0;  in sam9x60_div_pll_set_div()
284 			AT91_PMC_PLL_UPDT_ID_MASK, core->id);  in sam9x60_div_pll_set_div()
287 			core->layout->div_mask | enable_mask,  in sam9x60_div_pll_set_div()
288 			SHIFT_U32(div, core->layout->div_shift) | ena_val);  in sam9x60_div_pll_set_div()
292 			AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_div_pll_set_div()
294 	if (WAIT_PLL_READY_TIMEOUT(regmap, core->id)) {  in sam9x60_div_pll_set_div()
304 	struct sam9x60_pll_core *core = &div->core;  in sam9x60_div_pll_set()  local
305 	vaddr_t regmap = core->base;  in sam9x60_div_pll_set()
310 			AT91_PMC_PLL_UPDT_ID_MASK, core->id);  in sam9x60_div_pll_set()
312 	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;  in sam9x60_div_pll_set()
315 	if ((val & core->layout->endiv_mask) && cdiv == div->div)  in sam9x60_div_pll_set()
318 	return sam9x60_div_pll_set_div(core, div->div, 1);  in sam9x60_div_pll_set()
331 	struct sam9x60_pll_core *core = &div->core;  in sam9x60_div_pll_unprepare()  local
332 	vaddr_t regmap = core->base;  in sam9x60_div_pll_unprepare()
335 			AT91_PMC_PLL_UPDT_ID_MASK, core->id);  in sam9x60_div_pll_unprepare()
337 	io_clrbits32(regmap + AT91_PMC_PLL_CTRL0, core->layout->endiv_mask);  in sam9x60_div_pll_unprepare()
341 			AT91_PMC_PLL_UPDT_UPDATE | core->id);  in sam9x60_div_pll_unprepare()
371 	struct sam9x60_pll_core *core = &div->core;  in sam9x60_div_pll_set_rate_chg()  local
372 	vaddr_t regmap = core->base;  in sam9x60_div_pll_set_rate_chg()
383 			core->id);  in sam9x60_div_pll_set_rate_chg()
385 	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;  in sam9x60_div_pll_set_rate_chg()
391 	return sam9x60_div_pll_set_div(core, div->div, 0);  in sam9x60_div_pll_set_rate_chg()
434 	frac->core.id = id;  in sam9x60_clk_register_frac_pll()
435 	frac->core.charac = charac;  in sam9x60_clk_register_frac_pll()
436 	frac->core.layout = layout;  in sam9x60_clk_register_frac_pll()
437 	frac->core.base = pmc->base;  in sam9x60_clk_register_frac_pll()
440 		io_clrsetbits32(frac->core.base + AT91_PMC_PLL_UPDT,  in sam9x60_clk_register_frac_pll()
472 	frac->core.hw = hw;  in sam9x60_clk_register_frac_pll()
513 	div->core.id = id;  in sam9x60_clk_register_div_pll()
514 	div->core.charac = charac;  in sam9x60_clk_register_div_pll()
515 	div->core.layout = layout;  in sam9x60_clk_register_div_pll()
516 	div->core.base = pmc->base;  in sam9x60_clk_register_div_pll()
524 	div->core.hw = hw;  in sam9x60_clk_register_div_pll()