1*1bb92983SJerome Forissier /* SPDX-License-Identifier: BSD-2-Clause */ 27176a0b4SJoseph Chen /* 37176a0b4SJoseph Chen * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd. 47176a0b4SJoseph Chen */ 57176a0b4SJoseph Chen 67176a0b4SJoseph Chen #ifndef PLAT_ROCKCHIP_CRU_H 77176a0b4SJoseph Chen #define PLAT_ROCKCHIP_CRU_H 87176a0b4SJoseph Chen 9110da4bcSJoseph Chen #include <common.h> 107176a0b4SJoseph Chen #include <platform_config.h> 117176a0b4SJoseph Chen 127176a0b4SJoseph Chen #if defined(PLATFORM_FLAVOR_rk322x) 13110da4bcSJoseph Chen 14110da4bcSJoseph Chen enum plls_id { 15110da4bcSJoseph Chen APLL_ID, 16110da4bcSJoseph Chen DPLL_ID, 17110da4bcSJoseph Chen CPLL_ID, 18110da4bcSJoseph Chen GPLL_ID, 19110da4bcSJoseph Chen PLL_END, 20110da4bcSJoseph Chen }; 21110da4bcSJoseph Chen 227176a0b4SJoseph Chen #define CRU_SOFTRST_CON(i) (0x110 + ((i) * 4)) 237176a0b4SJoseph Chen #define CRU_MODE_CON 0x040 247176a0b4SJoseph Chen #define CRU_GLBRST_CFG_BASE 0x140 257176a0b4SJoseph Chen #define CRU_FSTRST_VAL_BASE 0x1f0 267176a0b4SJoseph Chen #define CRU_SNDRST_VAL_BASE 0x1f4 277176a0b4SJoseph Chen #define CRU_FSTRST_VAL 0xfdb9 287176a0b4SJoseph Chen #define CRU_SNDRST_VAL 0xeca8 297176a0b4SJoseph Chen #define PLLS_SLOW_MODE 0x11030000 307176a0b4SJoseph Chen 317176a0b4SJoseph Chen #define CORE_SOFT_RESET(core) SHIFT_U32(0x100010, (core)) 327176a0b4SJoseph Chen #define CORE_SOFT_RELEASE(core) SHIFT_U32(0x100000, (core)) 337176a0b4SJoseph Chen #define CORE_HELD_IN_RESET(core) SHIFT_U32(0x000010, (core)) 347176a0b4SJoseph Chen #define NONBOOT_CORES_SOFT_RESET 0x00e000e0 35110da4bcSJoseph Chen 36110da4bcSJoseph Chen #define CRU_CLKGATE_CON_CNT 16 37110da4bcSJoseph Chen #define CRU_CLKSEL_CON(i) (0x044 + ((i) * 4)) 38110da4bcSJoseph Chen #define CRU_CLKGATE_CON(i) (0x0d0 + ((i) * 4)) 39110da4bcSJoseph Chen #define CRU_PLL_CON0(pll) ((pll) * 0x0c + 0x0) 40110da4bcSJoseph Chen #define CRU_PLL_CON1(pll) ((pll) * 0x0c + 0x4) 41110da4bcSJoseph Chen #define CRU_PLL_CON2(pll) ((pll) * 0x0c + 0x8) 42110da4bcSJoseph Chen 43110da4bcSJoseph Chen #define PLL_LOCK BIT(10) 44110da4bcSJoseph Chen #define PLL_POWER_UP BITS_WITH_WMASK(0, 1, 13) 45110da4bcSJoseph Chen #define PLL_POWER_DOWN BITS_WITH_WMASK(1, 1, 13) 46110da4bcSJoseph Chen 47110da4bcSJoseph Chen #define PLL_MODE_BIT(pll) ((pll) * 4) 48110da4bcSJoseph Chen #define PLL_MODE_MSK(pll) BIT(PLL_MODE_BIT(pll)) 49110da4bcSJoseph Chen #define PLL_SLOW_MODE(pll) BITS_WITH_WMASK(0, 1, PLL_MODE_BIT(pll)) 50110da4bcSJoseph Chen #define PLL_NORM_MODE(pll) BITS_WITH_WMASK(1, 1, PLL_MODE_BIT(pll)) 517176a0b4SJoseph Chen #endif 527176a0b4SJoseph Chen 537176a0b4SJoseph Chen #endif 54