1PLATFORM_FLAVOR ?= ls1012ardb 2 3$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 4$(call force,CFG_GIC,y) 5$(call force,CFG_16550_UART,y) 6$(call force,CFG_LS,y) 7 8$(call force,CFG_DRAM0_BASE,0x80000000) 9$(call force,CFG_TEE_OS_DRAM0_SIZE,0x4000000) 10 11CFG_ENABLE_EMBEDDED_TESTS ?= y 12CFG_PKCS11_TA ?= y 13 14CFG_CORE_HEAP_SIZE ?= 131072 15 16ifeq ($(PLATFORM_FLAVOR),ls1012ardb) 17include core/arch/arm/cpu/cortex-armv8-0.mk 18$(call force,CFG_TEE_CORE_NB_CORE,1) 19$(call force,CFG_DRAM0_SIZE,0x40000000) 20$(call force,CFG_CORE_CLUSTER_SHIFT,2) 21CFG_NUM_THREADS ?= 2 22CFG_SHMEM_SIZE ?= 0x00200000 23endif 24 25ifeq ($(PLATFORM_FLAVOR),ls1043ardb) 26include core/arch/arm/cpu/cortex-armv8-0.mk 27$(call force,CFG_TEE_CORE_NB_CORE,4) 28$(call force,CFG_DRAM0_SIZE,0x80000000) 29$(call force,CFG_CORE_CLUSTER_SHIFT,2) 30CFG_SHMEM_SIZE ?= 0x00200000 31endif 32 33ifeq ($(PLATFORM_FLAVOR),ls1046ardb) 34include core/arch/arm/cpu/cortex-armv8-0.mk 35$(call force,CFG_TEE_CORE_NB_CORE,4) 36$(call force,CFG_DRAM0_SIZE,0x80000000) 37$(call force,CFG_CORE_CLUSTER_SHIFT,2) 38CFG_SHMEM_SIZE ?= 0x00200000 39endif 40 41ifeq ($(PLATFORM_FLAVOR),ls1088ardb) 42include core/arch/arm/cpu/cortex-armv8-0.mk 43$(call force,CFG_TEE_CORE_NB_CORE,8) 44$(call force,CFG_DRAM0_SIZE,0x80000000) 45$(call force,CFG_CORE_CLUSTER_SHIFT,2) 46$(call force,CFG_ARM_GICV3,y) 47CFG_SHMEM_SIZE ?= 0x00200000 48endif 49 50ifeq ($(PLATFORM_FLAVOR),ls2088ardb) 51include core/arch/arm/cpu/cortex-armv8-0.mk 52$(call force,CFG_TEE_CORE_NB_CORE,8) 53$(call force,CFG_DRAM0_SIZE,0x80000000) 54$(call force,CFG_CORE_CLUSTER_SHIFT,1) 55$(call force,CFG_ARM_GICV3,y) 56CFG_SHMEM_SIZE ?= 0x00200000 57endif 58 59ifeq ($(PLATFORM_FLAVOR),lx2160aqds) 60include core/arch/arm/cpu/cortex-armv8-0.mk 61$(call force,CFG_TEE_CORE_NB_CORE,16) 62$(call force,CFG_DRAM0_SIZE,0x80000000) 63$(call force,CFG_DRAM1_BASE,0x2080000000) 64$(call force,CFG_DRAM1_SIZE,0x1F80000000) 65$(call force,CFG_CORE_CLUSTER_SHIFT,1) 66$(call force,CFG_ARM_GICV3,y) 67$(call force,CFG_PL011,y) 68$(call force,CFG_CORE_ARM64_PA_BITS,40) 69$(call force,CFG_EMBED_DTB,y) 70$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-qds.dts) 71CFG_LS_I2C ?= y 72CFG_LS_GPIO ?= y 73CFG_LS_DSPI ?= y 74CFG_SHMEM_SIZE ?= 0x00200000 75endif 76 77ifeq ($(PLATFORM_FLAVOR),lx2160ardb) 78include core/arch/arm/cpu/cortex-armv8-0.mk 79$(call force,CFG_TEE_CORE_NB_CORE,16) 80$(call force,CFG_DRAM0_SIZE,0x80000000) 81$(call force,CFG_DRAM1_BASE,0x2080000000) 82$(call force,CFG_DRAM1_SIZE,0x1F80000000) 83$(call force,CFG_CORE_CLUSTER_SHIFT,1) 84$(call force,CFG_ARM_GICV3,y) 85$(call force,CFG_PL011,y) 86$(call force,CFG_CORE_ARM64_PA_BITS,40) 87$(call force,CFG_EMBED_DTB,y) 88$(call force,CFG_EMBED_DTB_SOURCE_FILE,fsl-lx2160a-rdb.dts) 89CFG_LS_I2C ?= y 90CFG_LS_GPIO ?= y 91CFG_LS_DSPI ?= y 92CFG_SHMEM_SIZE ?= 0x00200000 93endif 94 95ifeq ($(PLATFORM_FLAVOR),ls1028ardb) 96include core/arch/arm/cpu/cortex-armv8-0.mk 97$(call force,CFG_TEE_CORE_NB_CORE,2) 98$(call force,CFG_DRAM0_SIZE,0x80000000) 99$(call force,CFG_CORE_CLUSTER_SHIFT,1) 100$(call force,CFG_ARM_GICV3,y) 101CFG_SHMEM_SIZE ?= 0x00200000 102endif 103 104ifeq ($(platform-flavor-armv8),1) 105$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 106CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 107CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - CFG_SHMEM_SIZE) 108#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 109CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_SHMEM_SIZE) 110$(call force,CFG_ARM64_core,y) 111CFG_USER_TA_TARGETS ?= ta_arm64 112else 113#In ARMv7 platform CFG_SHMEM_SIZE is different to that of ARMv8 platforms. 114CFG_TZDRAM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - CFG_TEE_OS_DRAM0_SIZE) 115CFG_TZDRAM_SIZE ?= ( CFG_TEE_OS_DRAM0_SIZE - (2*CFG_SHMEM_SIZE)) 116#CFG_SHMEM_START (Non-Secure shared memory) needs to be 2MB aligned boundary for TZASC 380 configuration. 117CFG_SHMEM_START ?= ((CFG_DRAM0_BASE + CFG_DRAM0_SIZE) - (2*CFG_SHMEM_SIZE)) 118endif 119 120#Keeping Number of TEE thread equal to number of cores on the SoC 121CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE) 122 123ifneq ($(CFG_ARM64_core),y) 124$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 125endif 126 127CFG_CRYPTO_SIZE_OPTIMIZATION ?= n 128 129# NXP CAAM support is not enabled by default and can be enabled 130# on the command line 131CFG_NXP_CAAM ?= n 132