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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi21 #size-cells = <0>;
23 cpu@0 {
26 reg = <0x0>;
28 d-cache-size = <0x8000>;
31 i-cache-size = <0xc000>;
40 reg = <0x1>;
42 d-cache-size = <0x8000>;
45 i-cache-size = <0xc000>;
54 reg = <0x2>;
56 d-cache-size = <0x8000>;
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/wm8350/
H A Dpmic.h19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dpcm030.dts28 cell-index = <0>;
59 phy0: ethernet-phy@0 {
60 reg = <0>;
67 reg = <0x51>;
71 reg = <0x52>;
78 reg = <0x8000 0x4000>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
85 0xc000 0 0 2 &mpc5200_pic 1 1 3
86 0xc000 0 0 3 &mpc5200_pic 1 2 3
[all …]
H A Dmedia5200.dts28 PowerPC,5200@0 {
35 memory@0 {
36 reg = <0x00000000 0x08000000>; // 128MB RAM
72 phy0: ethernet-phy@0 {
73 reg = <0>;
78 reg = <0x1000 0x100>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85 0xc000 0 0 2 &media5200_fpga 0 3
86 0xc000 0 0 3 &media5200_fpga 0 4
[all …]
H A Ddigsy_mtc.dts19 memory@0 {
20 reg = <0x00000000 0x02000000>; // 32MB
29 msp430@0 {
32 reg = <0>;
65 phy0: ethernet-phy@0 {
66 reg = <0>;
73 reg = <0x50>;
78 reg = <0x56>;
83 reg = <0x68>;
93 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dmpc834x_mds.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe2400000 0x8000>;
57 ranges = <0x0 0xe0000000 0x00100000>;
58 reg = <0xe0000000 0x00000200>;
[all …]
H A Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
H A Dlite5200b.dts22 gpios = <&gpt2 0 1>;
25 gpios = <&gpt3 0 1>;
34 memory@0 {
35 reg = <0x00000000 0x10000000>; // 256MB
41 cell-index = <0>;
87 phy0: ethernet-phy@0 {
88 reg = <0>;
95 reg = <0x50>;
101 reg = <0x8000 0x4000>;
106 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
H A Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
H A Dpq2fads.dts26 #size-cells = <0>;
28 cpu@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x60>;
52 ranges = <0x0 0x0 0xff800000 0x800000
53 0x1 0x0 0xf4500000 0x8000
54 0x8 0x0 0xf8200000 0x8000>;
[all …]
H A Dmpc8272ads.dts25 #size-cells = <0>;
27 PowerPC,8272@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x0 0x0>;
50 reg = <0xf0010100 0x40>;
52 ranges = <0x0 0x0 0xff800000 0x00800000
53 0x1 0x0 0xf4500000 0x8000
[all …]
/OK3568_Linux_fs/kernel/sound/soc/qcom/
H A Dlpass-sc7180.c80 int chan = 0; in sc7180_lpass_alloc_dma_channel()
120 return 0; in sc7180_lpass_free_dma_channel()
134 for (i = 0; i < drvdata->num_clks; i++) in sc7180_lpass_init()
149 return 0; in sc7180_lpass_init()
158 return 0; in sc7180_lpass_exit()
162 .i2sctrl_reg_base = 0x1000,
163 .i2sctrl_reg_stride = 0x1000,
165 .irq_reg_base = 0x9000,
166 .irq_reg_stride = 0x1000,
168 .rdma_reg_base = 0xC000,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/marvell/
H A Darmada-ap806-quad.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0x000>;
24 clocks = <&cpu_clk 0>;
25 i-cache-size = <0xc000>;
28 d-cache-size = <0x8000>;
36 reg = <0x001>;
39 clocks = <&cpu_clk 0>;
40 i-cache-size = <0xc000>;
43 d-cache-size = <0x8000>;
[all …]
H A Darmada-ap807-quad.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0x000>;
24 clocks = <&cpu_clk 0>;
25 i-cache-size = <0xc000>;
28 d-cache-size = <0x8000>;
36 reg = <0x001>;
39 clocks = <&cpu_clk 0>;
40 i-cache-size = <0xc000>;
43 d-cache-size = <0x8000>;
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dlibata.h54 ATA_PIO0 = (1 << 0),
62 ATA_SWDMA0 = (1 << 0),
68 ATA_MWDMA0 = (1 << 0),
75 ATA_UDMA0 = (1 << 0),
94 ATA_DMA_CMD = 0,
96 ATA_DMA_START = (1 << 0),
99 ATA_DMA_ACTIVE = (1 << 0),
112 ATA_ERR = (1 << 0), /* have an error */
120 ATA_REG_DATA = 0x00,
121 ATA_REG_ERR = 0x01,
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Data.h22 #define ATA_DMA_BOUNDARY 0xffffUL
23 #define ATA_DMA_MASK 0xffffffffULL
38 ATA_ID_CONFIG = 0,
104 ATA_PIO0 = (1 << 0),
114 ATA_SWDMA0 = (1 << 0),
120 ATA_MWDMA0 = (1 << 0),
129 ATA_UDMA0 = (1 << 0),
150 ATA_DMA_CMD = 0,
152 ATA_DMA_START = (1 << 0),
155 ATA_DMA_ACTIVE = (1 << 0),
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Drt1308-sdw.h12 { 0x0000, 0x00 },
13 { 0x0001, 0x00 },
14 { 0x0002, 0x00 },
15 { 0x0003, 0x00 },
16 { 0x0004, 0x00 },
17 { 0x0005, 0x01 },
18 { 0x0020, 0x00 },
19 { 0x0022, 0x00 },
20 { 0x0023, 0x00 },
21 { 0x0024, 0x00 },
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a.dtsi11 /memreserve/ 0x80000000 0x00010000;
25 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
34 d-cache-size = <0x8000>;
37 i-cache-size = <0xC000>;
49 reg = <0x1>;
50 clocks = <&clockgen 1 0>;
51 d-cache-size = <0x8000>;
[all …]
/OK3568_Linux_fs/u-boot/configs/
H A Drv1126-spi-nor-tb.config17 CONFIG_SYS_MALLOC_F_LEN=0xc000
18 CONFIG_TPL_SYS_MALLOC_F_LEN=0xc000
/OK3568_Linux_fs/kernel/arch/csky/kernel/probes/
H A Ddecode-insn.h15 #define is_insn32(insn) ((insn & 0xc000) == 0xc000)
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dau8522_common.c22 } while (0)
33 u8 buf[] = { (reg >> 8) | 0x80, reg & 0xff, data }; in au8522_writereg()
36 .flags = 0, .buf = buf, .len = 3 }; in au8522_writereg()
41 printk("%s: writereg error (reg == 0x%02x, val == 0x%04x, ret == %i)\n", in au8522_writereg()
44 return (ret != 1) ? -1 : 0; in au8522_writereg()
51 u8 b0[] = { (reg >> 8) | 0x40, reg & 0xff }; in au8522_readreg()
52 u8 b1[] = { 0 }; in au8522_readreg()
55 { .addr = state->config.demod_address, .flags = 0, in au8522_readreg()
65 return b1[0]; in au8522_readreg()
80 return 0; in au8522_i2c_gate_ctrl()
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dmv88e6352.c13 #define SMI_HDR ((0x8 | 0x1) << 12)
14 #define SMI_BUSY_MASK (0x8000)
15 #define SMIRD_OP (0x2 << 10)
16 #define SMIWR_OP (0x1 << 10)
17 #define SMI_MASK 0x1f
20 #define COMMAND_REG 0
24 #define GLOBAL 0x1b
26 #define GLOBAL_STATUS 0x00
27 #define PPU_STATE 0x8000
29 #define GLOBAL_CTRL 0x04
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/wm831x/
H A Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]

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