Lines Matching +full:0 +full:xc000
80 int chan = 0; in sc7180_lpass_alloc_dma_channel()
120 return 0; in sc7180_lpass_free_dma_channel()
134 for (i = 0; i < drvdata->num_clks; i++) in sc7180_lpass_init()
149 return 0; in sc7180_lpass_init()
158 return 0; in sc7180_lpass_exit()
162 .i2sctrl_reg_base = 0x1000,
163 .i2sctrl_reg_stride = 0x1000,
165 .irq_reg_base = 0x9000,
166 .irq_reg_stride = 0x1000,
168 .rdma_reg_base = 0xC000,
169 .rdma_reg_stride = 0x1000,
171 .hdmi_rdma_reg_base = 0x64000,
172 .hdmi_rdma_reg_stride = 0x1000,
175 .wrdma_reg_base = 0x18000,
176 .wrdma_reg_stride = 0x1000,
180 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
181 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
182 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
183 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
184 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
185 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
186 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
187 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
188 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
190 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
191 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
192 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
193 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
194 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
195 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
197 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
198 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
199 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
200 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
201 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
202 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
204 .hdmi_tx_ctl_addr = 0x1000,
205 .hdmi_legacy_addr = 0x1008,
206 .hdmi_vbit_addr = 0x610c0,
207 .hdmi_ch_lsb_addr = 0x61048,
208 .hdmi_ch_msb_addr = 0x6104c,
209 .ch_stride = 0x8,
210 .hdmi_parity_addr = 0x61034,
211 .hdmi_dmactl_addr = 0x61038,
212 .hdmi_dma_stride = 0x4,
213 .hdmi_DP_addr = 0x610c8,
214 .hdmi_sstream_addr = 0x6101c,
215 .hdmi_irq_reg_base = 0x63000,
218 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
219 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
220 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
221 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
222 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
223 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
224 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
225 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
227 .sstream_en = REG_FIELD(0x6101c, 0, 0),
228 .dma_sel = REG_FIELD(0x6101c, 1, 2),
229 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
230 .layout = REG_FIELD(0x6101c, 4, 4),
231 .layout_sp = REG_FIELD(0x6101c, 5, 8),
232 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
233 .dp_audio = REG_FIELD(0x6101c, 11, 11),
234 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
235 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
237 .mute = REG_FIELD(0x610c8, 0, 0),
238 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
239 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
240 .aif_db4 = REG_FIELD(0x610c8, 8, 15),
241 .frequency = REG_FIELD(0x610c8, 16, 21),
242 .mst_index = REG_FIELD(0x610c8, 28, 29),
243 .dptx_index = REG_FIELD(0x610c8, 30, 31),
245 .soft_reset = REG_FIELD(0x1000, 31, 31),
246 .force_reset = REG_FIELD(0x1000, 30, 30),
248 .use_hw_chs = REG_FIELD(0x61038, 0, 0),
249 .use_hw_usr = REG_FIELD(0x61038, 1, 1),
250 .hw_chs_sel = REG_FIELD(0x61038, 2, 4),
251 .hw_usr_sel = REG_FIELD(0x61038, 5, 6),
253 .replace_vbit = REG_FIELD(0x610c0, 0, 0),
254 .vbit_stream = REG_FIELD(0x610c0, 1, 1),
256 .legacy_en = REG_FIELD(0x1008, 0, 0),
257 .calc_en = REG_FIELD(0x61034, 0, 0),
258 .lsb_bits = REG_FIELD(0x61048, 0, 31),
259 .msb_bits = REG_FIELD(0x6104c, 0, 31),