xref: /OK3568_Linux_fs/kernel/include/linux/mfd/wm8350/pmic.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * pmic.h  --  Power Management Driver for Wolfson WM8350 PMIC
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2007 Wolfson Microelectronics PLC
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __LINUX_MFD_WM8350_PMIC_H
9*4882a593Smuzhiyun #define __LINUX_MFD_WM8350_PMIC_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/leds.h>
13*4882a593Smuzhiyun #include <linux/regulator/machine.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun  * Register values.
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define WM8350_CURRENT_SINK_DRIVER_A            0xAC
20*4882a593Smuzhiyun #define WM8350_CSA_FLASH_CONTROL                0xAD
21*4882a593Smuzhiyun #define WM8350_CURRENT_SINK_DRIVER_B            0xAE
22*4882a593Smuzhiyun #define WM8350_CSB_FLASH_CONTROL                0xAF
23*4882a593Smuzhiyun #define WM8350_DCDC_LDO_REQUESTED               0xB0
24*4882a593Smuzhiyun #define WM8350_DCDC_ACTIVE_OPTIONS              0xB1
25*4882a593Smuzhiyun #define WM8350_DCDC_SLEEP_OPTIONS               0xB2
26*4882a593Smuzhiyun #define WM8350_POWER_CHECK_COMPARATOR           0xB3
27*4882a593Smuzhiyun #define WM8350_DCDC1_CONTROL                    0xB4
28*4882a593Smuzhiyun #define WM8350_DCDC1_TIMEOUTS                   0xB5
29*4882a593Smuzhiyun #define WM8350_DCDC1_LOW_POWER                  0xB6
30*4882a593Smuzhiyun #define WM8350_DCDC2_CONTROL                    0xB7
31*4882a593Smuzhiyun #define WM8350_DCDC2_TIMEOUTS                   0xB8
32*4882a593Smuzhiyun #define WM8350_DCDC3_CONTROL                    0xBA
33*4882a593Smuzhiyun #define WM8350_DCDC3_TIMEOUTS                   0xBB
34*4882a593Smuzhiyun #define WM8350_DCDC3_LOW_POWER                  0xBC
35*4882a593Smuzhiyun #define WM8350_DCDC4_CONTROL                    0xBD
36*4882a593Smuzhiyun #define WM8350_DCDC4_TIMEOUTS                   0xBE
37*4882a593Smuzhiyun #define WM8350_DCDC4_LOW_POWER                  0xBF
38*4882a593Smuzhiyun #define WM8350_DCDC5_CONTROL                    0xC0
39*4882a593Smuzhiyun #define WM8350_DCDC5_TIMEOUTS                   0xC1
40*4882a593Smuzhiyun #define WM8350_DCDC6_CONTROL                    0xC3
41*4882a593Smuzhiyun #define WM8350_DCDC6_TIMEOUTS                   0xC4
42*4882a593Smuzhiyun #define WM8350_DCDC6_LOW_POWER                  0xC5
43*4882a593Smuzhiyun #define WM8350_LIMIT_SWITCH_CONTROL             0xC7
44*4882a593Smuzhiyun #define WM8350_LDO1_CONTROL                     0xC8
45*4882a593Smuzhiyun #define WM8350_LDO1_TIMEOUTS                    0xC9
46*4882a593Smuzhiyun #define WM8350_LDO1_LOW_POWER                   0xCA
47*4882a593Smuzhiyun #define WM8350_LDO2_CONTROL                     0xCB
48*4882a593Smuzhiyun #define WM8350_LDO2_TIMEOUTS                    0xCC
49*4882a593Smuzhiyun #define WM8350_LDO2_LOW_POWER                   0xCD
50*4882a593Smuzhiyun #define WM8350_LDO3_CONTROL                     0xCE
51*4882a593Smuzhiyun #define WM8350_LDO3_TIMEOUTS                    0xCF
52*4882a593Smuzhiyun #define WM8350_LDO3_LOW_POWER                   0xD0
53*4882a593Smuzhiyun #define WM8350_LDO4_CONTROL                     0xD1
54*4882a593Smuzhiyun #define WM8350_LDO4_TIMEOUTS                    0xD2
55*4882a593Smuzhiyun #define WM8350_LDO4_LOW_POWER                   0xD3
56*4882a593Smuzhiyun #define WM8350_VCC_FAULT_MASKS                  0xD7
57*4882a593Smuzhiyun #define WM8350_MAIN_BANDGAP_CONTROL             0xD8
58*4882a593Smuzhiyun #define WM8350_OSC_CONTROL                      0xD9
59*4882a593Smuzhiyun #define WM8350_RTC_TICK_CONTROL                 0xDA
60*4882a593Smuzhiyun #define WM8350_SECURITY                         0xDB
61*4882a593Smuzhiyun #define WM8350_RAM_BIST_1                       0xDC
62*4882a593Smuzhiyun #define WM8350_DCDC_LDO_STATUS                  0xE1
63*4882a593Smuzhiyun #define WM8350_GPIO_PIN_STATUS                  0xE6
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define WM8350_DCDC1_FORCE_PWM                  0xF8
66*4882a593Smuzhiyun #define WM8350_DCDC3_FORCE_PWM                  0xFA
67*4882a593Smuzhiyun #define WM8350_DCDC4_FORCE_PWM                  0xFB
68*4882a593Smuzhiyun #define WM8350_DCDC6_FORCE_PWM                  0xFD
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun  * R172 (0xAC) - Current Sink Driver A
72*4882a593Smuzhiyun  */
73*4882a593Smuzhiyun #define WM8350_CS1_HIB_MODE                     0x1000
74*4882a593Smuzhiyun #define WM8350_CS1_HIB_MODE_MASK                0x1000
75*4882a593Smuzhiyun #define WM8350_CS1_HIB_MODE_SHIFT                   12
76*4882a593Smuzhiyun #define WM8350_CS1_ISEL_MASK                    0x003F
77*4882a593Smuzhiyun #define WM8350_CS1_ISEL_SHIFT                        0
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /* Bit values for R172 (0xAC) */
80*4882a593Smuzhiyun #define WM8350_CS1_HIB_MODE_DISABLE                  0
81*4882a593Smuzhiyun #define WM8350_CS1_HIB_MODE_LEAVE                    1
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define WM8350_CS1_ISEL_220M                      0x3F
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun  * R173 (0xAD) - CSA Flash control
87*4882a593Smuzhiyun  */
88*4882a593Smuzhiyun #define WM8350_CS1_FLASH_MODE                   0x8000
89*4882a593Smuzhiyun #define WM8350_CS1_TRIGSRC                      0x4000
90*4882a593Smuzhiyun #define WM8350_CS1_DRIVE                        0x2000
91*4882a593Smuzhiyun #define WM8350_CS1_FLASH_DUR_MASK               0x0300
92*4882a593Smuzhiyun #define WM8350_CS1_OFF_RAMP_MASK                0x0030
93*4882a593Smuzhiyun #define WM8350_CS1_ON_RAMP_MASK                 0x0003
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun  * R174 (0xAE) - Current Sink Driver B
97*4882a593Smuzhiyun  */
98*4882a593Smuzhiyun #define WM8350_CS2_HIB_MODE                     0x1000
99*4882a593Smuzhiyun #define WM8350_CS2_ISEL_MASK                    0x003F
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun  * R175 (0xAF) - CSB Flash control
103*4882a593Smuzhiyun  */
104*4882a593Smuzhiyun #define WM8350_CS2_FLASH_MODE                   0x8000
105*4882a593Smuzhiyun #define WM8350_CS2_TRIGSRC                      0x4000
106*4882a593Smuzhiyun #define WM8350_CS2_DRIVE                        0x2000
107*4882a593Smuzhiyun #define WM8350_CS2_FLASH_DUR_MASK               0x0300
108*4882a593Smuzhiyun #define WM8350_CS2_OFF_RAMP_MASK                0x0030
109*4882a593Smuzhiyun #define WM8350_CS2_ON_RAMP_MASK                 0x0003
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun  * R176 (0xB0) - DCDC/LDO requested
113*4882a593Smuzhiyun  */
114*4882a593Smuzhiyun #define WM8350_LS_ENA                           0x8000
115*4882a593Smuzhiyun #define WM8350_LDO4_ENA                         0x0800
116*4882a593Smuzhiyun #define WM8350_LDO3_ENA                         0x0400
117*4882a593Smuzhiyun #define WM8350_LDO2_ENA                         0x0200
118*4882a593Smuzhiyun #define WM8350_LDO1_ENA                         0x0100
119*4882a593Smuzhiyun #define WM8350_DC6_ENA                          0x0020
120*4882a593Smuzhiyun #define WM8350_DC5_ENA                          0x0010
121*4882a593Smuzhiyun #define WM8350_DC4_ENA                          0x0008
122*4882a593Smuzhiyun #define WM8350_DC3_ENA                          0x0004
123*4882a593Smuzhiyun #define WM8350_DC2_ENA                          0x0002
124*4882a593Smuzhiyun #define WM8350_DC1_ENA                          0x0001
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /*
127*4882a593Smuzhiyun  * R177 (0xB1) - DCDC Active options
128*4882a593Smuzhiyun  */
129*4882a593Smuzhiyun #define WM8350_PUTO_MASK                        0x3000
130*4882a593Smuzhiyun #define WM8350_PWRUP_DELAY_MASK                 0x0300
131*4882a593Smuzhiyun #define WM8350_DC6_ACTIVE                       0x0020
132*4882a593Smuzhiyun #define WM8350_DC4_ACTIVE                       0x0008
133*4882a593Smuzhiyun #define WM8350_DC3_ACTIVE                       0x0004
134*4882a593Smuzhiyun #define WM8350_DC1_ACTIVE                       0x0001
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun /*
137*4882a593Smuzhiyun  * R178 (0xB2) - DCDC Sleep options
138*4882a593Smuzhiyun  */
139*4882a593Smuzhiyun #define WM8350_DC6_SLEEP                        0x0020
140*4882a593Smuzhiyun #define WM8350_DC4_SLEEP                        0x0008
141*4882a593Smuzhiyun #define WM8350_DC3_SLEEP                        0x0004
142*4882a593Smuzhiyun #define WM8350_DC1_SLEEP                        0x0001
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun /*
145*4882a593Smuzhiyun  * R179 (0xB3) - Power-check comparator
146*4882a593Smuzhiyun  */
147*4882a593Smuzhiyun #define WM8350_PCCMP_ERRACT                     0x4000
148*4882a593Smuzhiyun #define WM8350_PCCMP_RAIL                       0x0100
149*4882a593Smuzhiyun #define WM8350_PCCMP_OFF_THR_MASK               0x0070
150*4882a593Smuzhiyun #define WM8350_PCCMP_ON_THR_MASK                0x0007
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /*
153*4882a593Smuzhiyun  * R180 (0xB4) - DCDC1 Control
154*4882a593Smuzhiyun  */
155*4882a593Smuzhiyun #define WM8350_DC1_OPFLT                        0x0400
156*4882a593Smuzhiyun #define WM8350_DC1_VSEL_MASK                    0x007F
157*4882a593Smuzhiyun #define WM8350_DC1_VSEL_SHIFT                        0
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun /*
160*4882a593Smuzhiyun  * R181 (0xB5) - DCDC1 Timeouts
161*4882a593Smuzhiyun  */
162*4882a593Smuzhiyun #define WM8350_DC1_ERRACT_MASK                  0xC000
163*4882a593Smuzhiyun #define WM8350_DC1_ERRACT_SHIFT                     14
164*4882a593Smuzhiyun #define WM8350_DC1_ENSLOT_MASK                  0x3C00
165*4882a593Smuzhiyun #define WM8350_DC1_ENSLOT_SHIFT                     10
166*4882a593Smuzhiyun #define WM8350_DC1_SDSLOT_MASK                  0x03C0
167*4882a593Smuzhiyun #define WM8350_DC1_UVTO_MASK                    0x0030
168*4882a593Smuzhiyun #define WM8350_DC1_SDSLOT_SHIFT                      6
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /* Bit values for R181 (0xB5) */
171*4882a593Smuzhiyun #define WM8350_DC1_ERRACT_NONE                       0
172*4882a593Smuzhiyun #define WM8350_DC1_ERRACT_SHUTDOWN_CONV              1
173*4882a593Smuzhiyun #define WM8350_DC1_ERRACT_SHUTDOWN_SYS               2
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun /*
176*4882a593Smuzhiyun  * R182 (0xB6) - DCDC1 Low Power
177*4882a593Smuzhiyun  */
178*4882a593Smuzhiyun #define WM8350_DC1_HIB_MODE_MASK                0x7000
179*4882a593Smuzhiyun #define WM8350_DC1_HIB_TRIG_MASK                0x0300
180*4882a593Smuzhiyun #define WM8350_DC1_VIMG_MASK                    0x007F
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun /*
183*4882a593Smuzhiyun  * R183 (0xB7) - DCDC2 Control
184*4882a593Smuzhiyun  */
185*4882a593Smuzhiyun #define WM8350_DC2_MODE                         0x4000
186*4882a593Smuzhiyun #define WM8350_DC2_MODE_MASK                    0x4000
187*4882a593Smuzhiyun #define WM8350_DC2_MODE_SHIFT                       14
188*4882a593Smuzhiyun #define WM8350_DC2_HIB_MODE                     0x1000
189*4882a593Smuzhiyun #define WM8350_DC2_HIB_MODE_MASK                0x1000
190*4882a593Smuzhiyun #define WM8350_DC2_HIB_MODE_SHIFT                   12
191*4882a593Smuzhiyun #define WM8350_DC2_HIB_TRIG_MASK                0x0300
192*4882a593Smuzhiyun #define WM8350_DC2_HIB_TRIG_SHIFT                    8
193*4882a593Smuzhiyun #define WM8350_DC2_ILIM                         0x0040
194*4882a593Smuzhiyun #define WM8350_DC2_ILIM_MASK                    0x0040
195*4882a593Smuzhiyun #define WM8350_DC2_ILIM_SHIFT                        6
196*4882a593Smuzhiyun #define WM8350_DC2_RMP_MASK                     0x0018
197*4882a593Smuzhiyun #define WM8350_DC2_RMP_SHIFT                         3
198*4882a593Smuzhiyun #define WM8350_DC2_FBSRC_MASK                   0x0003
199*4882a593Smuzhiyun #define WM8350_DC2_FBSRC_SHIFT                       0
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun /* Bit values for R183 (0xB7) */
202*4882a593Smuzhiyun #define WM8350_DC2_MODE_BOOST                        0
203*4882a593Smuzhiyun #define WM8350_DC2_MODE_SWITCH                       1
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #define WM8350_DC2_HIB_MODE_ACTIVE                   1
206*4882a593Smuzhiyun #define WM8350_DC2_HIB_MODE_DISABLE                  0
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun #define WM8350_DC2_HIB_TRIG_NONE                     0
209*4882a593Smuzhiyun #define WM8350_DC2_HIB_TRIG_LPWR1                    1
210*4882a593Smuzhiyun #define WM8350_DC2_HIB_TRIG_LPWR2                    2
211*4882a593Smuzhiyun #define WM8350_DC2_HIB_TRIG_LPWR3                    3
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun #define WM8350_DC2_ILIM_HIGH                         0
214*4882a593Smuzhiyun #define WM8350_DC2_ILIM_LOW                          1
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun #define WM8350_DC2_RMP_30V                           0
217*4882a593Smuzhiyun #define WM8350_DC2_RMP_20V                           1
218*4882a593Smuzhiyun #define WM8350_DC2_RMP_10V                           2
219*4882a593Smuzhiyun #define WM8350_DC2_RMP_5V                            3
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun #define WM8350_DC2_FBSRC_FB2                         0
222*4882a593Smuzhiyun #define WM8350_DC2_FBSRC_ISINKA                      1
223*4882a593Smuzhiyun #define WM8350_DC2_FBSRC_ISINKB                      2
224*4882a593Smuzhiyun #define WM8350_DC2_FBSRC_USB                         3
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun /*
227*4882a593Smuzhiyun  * R184 (0xB8) - DCDC2 Timeouts
228*4882a593Smuzhiyun  */
229*4882a593Smuzhiyun #define WM8350_DC2_ERRACT_MASK                  0xC000
230*4882a593Smuzhiyun #define WM8350_DC2_ERRACT_SHIFT                     14
231*4882a593Smuzhiyun #define WM8350_DC2_ENSLOT_MASK                  0x3C00
232*4882a593Smuzhiyun #define WM8350_DC2_ENSLOT_SHIFT                     10
233*4882a593Smuzhiyun #define WM8350_DC2_SDSLOT_MASK                  0x03C0
234*4882a593Smuzhiyun #define WM8350_DC2_UVTO_MASK                    0x0030
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun /* Bit values for R184 (0xB8) */
237*4882a593Smuzhiyun #define WM8350_DC2_ERRACT_NONE                       0
238*4882a593Smuzhiyun #define WM8350_DC2_ERRACT_SHUTDOWN_CONV              1
239*4882a593Smuzhiyun #define WM8350_DC2_ERRACT_SHUTDOWN_SYS               2
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun /*
242*4882a593Smuzhiyun  * R186 (0xBA) - DCDC3 Control
243*4882a593Smuzhiyun  */
244*4882a593Smuzhiyun #define WM8350_DC3_OPFLT                        0x0400
245*4882a593Smuzhiyun #define WM8350_DC3_VSEL_MASK                    0x007F
246*4882a593Smuzhiyun #define WM8350_DC3_VSEL_SHIFT                        0
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun /*
249*4882a593Smuzhiyun  * R187 (0xBB) - DCDC3 Timeouts
250*4882a593Smuzhiyun  */
251*4882a593Smuzhiyun #define WM8350_DC3_ERRACT_MASK                  0xC000
252*4882a593Smuzhiyun #define WM8350_DC3_ERRACT_SHIFT                     14
253*4882a593Smuzhiyun #define WM8350_DC3_ENSLOT_MASK                  0x3C00
254*4882a593Smuzhiyun #define WM8350_DC3_ENSLOT_SHIFT                     10
255*4882a593Smuzhiyun #define WM8350_DC3_SDSLOT_MASK                  0x03C0
256*4882a593Smuzhiyun #define WM8350_DC3_UVTO_MASK                    0x0030
257*4882a593Smuzhiyun #define WM8350_DC3_SDSLOT_SHIFT                      6
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun /* Bit values for R187 (0xBB) */
260*4882a593Smuzhiyun #define WM8350_DC3_ERRACT_NONE                       0
261*4882a593Smuzhiyun #define WM8350_DC3_ERRACT_SHUTDOWN_CONV              1
262*4882a593Smuzhiyun #define WM8350_DC3_ERRACT_SHUTDOWN_SYS               2
263*4882a593Smuzhiyun /*
264*4882a593Smuzhiyun  * R188 (0xBC) - DCDC3 Low Power
265*4882a593Smuzhiyun  */
266*4882a593Smuzhiyun #define WM8350_DC3_HIB_MODE_MASK                0x7000
267*4882a593Smuzhiyun #define WM8350_DC3_HIB_TRIG_MASK                0x0300
268*4882a593Smuzhiyun #define WM8350_DC3_VIMG_MASK                    0x007F
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun /*
271*4882a593Smuzhiyun  * R189 (0xBD) - DCDC4 Control
272*4882a593Smuzhiyun  */
273*4882a593Smuzhiyun #define WM8350_DC4_OPFLT                        0x0400
274*4882a593Smuzhiyun #define WM8350_DC4_VSEL_MASK                    0x007F
275*4882a593Smuzhiyun #define WM8350_DC4_VSEL_SHIFT                        0
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun /*
278*4882a593Smuzhiyun  * R190 (0xBE) - DCDC4 Timeouts
279*4882a593Smuzhiyun  */
280*4882a593Smuzhiyun #define WM8350_DC4_ERRACT_MASK                  0xC000
281*4882a593Smuzhiyun #define WM8350_DC4_ERRACT_SHIFT                     14
282*4882a593Smuzhiyun #define WM8350_DC4_ENSLOT_MASK                  0x3C00
283*4882a593Smuzhiyun #define WM8350_DC4_ENSLOT_SHIFT                     10
284*4882a593Smuzhiyun #define WM8350_DC4_SDSLOT_MASK                  0x03C0
285*4882a593Smuzhiyun #define WM8350_DC4_UVTO_MASK                    0x0030
286*4882a593Smuzhiyun #define WM8350_DC4_SDSLOT_SHIFT                      6
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun /* Bit values for R190 (0xBE) */
289*4882a593Smuzhiyun #define WM8350_DC4_ERRACT_NONE                       0
290*4882a593Smuzhiyun #define WM8350_DC4_ERRACT_SHUTDOWN_CONV              1
291*4882a593Smuzhiyun #define WM8350_DC4_ERRACT_SHUTDOWN_SYS               2
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun /*
294*4882a593Smuzhiyun  * R191 (0xBF) - DCDC4 Low Power
295*4882a593Smuzhiyun  */
296*4882a593Smuzhiyun #define WM8350_DC4_HIB_MODE_MASK                0x7000
297*4882a593Smuzhiyun #define WM8350_DC4_HIB_TRIG_MASK                0x0300
298*4882a593Smuzhiyun #define WM8350_DC4_VIMG_MASK                    0x007F
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun /*
301*4882a593Smuzhiyun  * R192 (0xC0) - DCDC5 Control
302*4882a593Smuzhiyun  */
303*4882a593Smuzhiyun #define WM8350_DC5_MODE                         0x4000
304*4882a593Smuzhiyun #define WM8350_DC5_MODE_MASK                    0x4000
305*4882a593Smuzhiyun #define WM8350_DC5_MODE_SHIFT                       14
306*4882a593Smuzhiyun #define WM8350_DC5_HIB_MODE                     0x1000
307*4882a593Smuzhiyun #define WM8350_DC5_HIB_MODE_MASK                0x1000
308*4882a593Smuzhiyun #define WM8350_DC5_HIB_MODE_SHIFT                   12
309*4882a593Smuzhiyun #define WM8350_DC5_HIB_TRIG_MASK                0x0300
310*4882a593Smuzhiyun #define WM8350_DC5_HIB_TRIG_SHIFT                    8
311*4882a593Smuzhiyun #define WM8350_DC5_ILIM                         0x0040
312*4882a593Smuzhiyun #define WM8350_DC5_ILIM_MASK                    0x0040
313*4882a593Smuzhiyun #define WM8350_DC5_ILIM_SHIFT                        6
314*4882a593Smuzhiyun #define WM8350_DC5_RMP_MASK                     0x0018
315*4882a593Smuzhiyun #define WM8350_DC5_RMP_SHIFT                         3
316*4882a593Smuzhiyun #define WM8350_DC5_FBSRC_MASK                   0x0003
317*4882a593Smuzhiyun #define WM8350_DC5_FBSRC_SHIFT                       0
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun /* Bit values for R192 (0xC0) */
320*4882a593Smuzhiyun #define WM8350_DC5_MODE_BOOST                        0
321*4882a593Smuzhiyun #define WM8350_DC5_MODE_SWITCH                       1
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun #define WM8350_DC5_HIB_MODE_ACTIVE                   1
324*4882a593Smuzhiyun #define WM8350_DC5_HIB_MODE_DISABLE                  0
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun #define WM8350_DC5_HIB_TRIG_NONE                     0
327*4882a593Smuzhiyun #define WM8350_DC5_HIB_TRIG_LPWR1                    1
328*4882a593Smuzhiyun #define WM8350_DC5_HIB_TRIG_LPWR2                    2
329*4882a593Smuzhiyun #define WM8350_DC5_HIB_TRIG_LPWR3                    3
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun #define WM8350_DC5_ILIM_HIGH                         0
332*4882a593Smuzhiyun #define WM8350_DC5_ILIM_LOW                          1
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun #define WM8350_DC5_RMP_30V                           0
335*4882a593Smuzhiyun #define WM8350_DC5_RMP_20V                           1
336*4882a593Smuzhiyun #define WM8350_DC5_RMP_10V                           2
337*4882a593Smuzhiyun #define WM8350_DC5_RMP_5V                            3
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun #define WM8350_DC5_FBSRC_FB2                         0
340*4882a593Smuzhiyun #define WM8350_DC5_FBSRC_ISINKA                      1
341*4882a593Smuzhiyun #define WM8350_DC5_FBSRC_ISINKB                      2
342*4882a593Smuzhiyun #define WM8350_DC5_FBSRC_USB                         3
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun /*
345*4882a593Smuzhiyun  * R193 (0xC1) - DCDC5 Timeouts
346*4882a593Smuzhiyun  */
347*4882a593Smuzhiyun #define WM8350_DC5_ERRACT_MASK                  0xC000
348*4882a593Smuzhiyun #define WM8350_DC5_ERRACT_SHIFT                     14
349*4882a593Smuzhiyun #define WM8350_DC5_ENSLOT_MASK                  0x3C00
350*4882a593Smuzhiyun #define WM8350_DC5_ENSLOT_SHIFT                     10
351*4882a593Smuzhiyun #define WM8350_DC5_SDSLOT_MASK                  0x03C0
352*4882a593Smuzhiyun #define WM8350_DC5_UVTO_MASK                    0x0030
353*4882a593Smuzhiyun #define WM8350_DC5_SDSLOT_SHIFT                      6
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun /* Bit values for R193 (0xC1) */
356*4882a593Smuzhiyun #define WM8350_DC5_ERRACT_NONE                       0
357*4882a593Smuzhiyun #define WM8350_DC5_ERRACT_SHUTDOWN_CONV              1
358*4882a593Smuzhiyun #define WM8350_DC5_ERRACT_SHUTDOWN_SYS               2
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun /*
361*4882a593Smuzhiyun  * R195 (0xC3) - DCDC6 Control
362*4882a593Smuzhiyun  */
363*4882a593Smuzhiyun #define WM8350_DC6_OPFLT                        0x0400
364*4882a593Smuzhiyun #define WM8350_DC6_VSEL_MASK                    0x007F
365*4882a593Smuzhiyun #define WM8350_DC6_VSEL_SHIFT                        0
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun /*
368*4882a593Smuzhiyun  * R196 (0xC4) - DCDC6 Timeouts
369*4882a593Smuzhiyun  */
370*4882a593Smuzhiyun #define WM8350_DC6_ERRACT_MASK                  0xC000
371*4882a593Smuzhiyun #define WM8350_DC6_ERRACT_SHIFT                     14
372*4882a593Smuzhiyun #define WM8350_DC6_ENSLOT_MASK                  0x3C00
373*4882a593Smuzhiyun #define WM8350_DC6_ENSLOT_SHIFT                     10
374*4882a593Smuzhiyun #define WM8350_DC6_SDSLOT_MASK                  0x03C0
375*4882a593Smuzhiyun #define WM8350_DC6_UVTO_MASK                    0x0030
376*4882a593Smuzhiyun #define WM8350_DC6_SDSLOT_SHIFT                      6
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun /* Bit values for R196 (0xC4) */
379*4882a593Smuzhiyun #define WM8350_DC6_ERRACT_NONE                       0
380*4882a593Smuzhiyun #define WM8350_DC6_ERRACT_SHUTDOWN_CONV              1
381*4882a593Smuzhiyun #define WM8350_DC6_ERRACT_SHUTDOWN_SYS               2
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun /*
384*4882a593Smuzhiyun  * R197 (0xC5) - DCDC6 Low Power
385*4882a593Smuzhiyun  */
386*4882a593Smuzhiyun #define WM8350_DC6_HIB_MODE_MASK                0x7000
387*4882a593Smuzhiyun #define WM8350_DC6_HIB_TRIG_MASK                0x0300
388*4882a593Smuzhiyun #define WM8350_DC6_VIMG_MASK                    0x007F
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun /*
391*4882a593Smuzhiyun  * R199 (0xC7) - Limit Switch Control
392*4882a593Smuzhiyun  */
393*4882a593Smuzhiyun #define WM8350_LS_ERRACT_MASK                   0xC000
394*4882a593Smuzhiyun #define WM8350_LS_ERRACT_SHIFT                      14
395*4882a593Smuzhiyun #define WM8350_LS_ENSLOT_MASK                   0x3C00
396*4882a593Smuzhiyun #define WM8350_LS_ENSLOT_SHIFT                      10
397*4882a593Smuzhiyun #define WM8350_LS_SDSLOT_MASK                   0x03C0
398*4882a593Smuzhiyun #define WM8350_LS_SDSLOT_SHIFT                       6
399*4882a593Smuzhiyun #define WM8350_LS_HIB_MODE                      0x0010
400*4882a593Smuzhiyun #define WM8350_LS_HIB_MODE_MASK                 0x0010
401*4882a593Smuzhiyun #define WM8350_LS_HIB_MODE_SHIFT                     4
402*4882a593Smuzhiyun #define WM8350_LS_HIB_PROT                      0x0002
403*4882a593Smuzhiyun #define WM8350_LS_HIB_PROT_MASK                 0x0002
404*4882a593Smuzhiyun #define WM8350_LS_HIB_PROT_SHIFT                     1
405*4882a593Smuzhiyun #define WM8350_LS_PROT                          0x0001
406*4882a593Smuzhiyun #define WM8350_LS_PROT_MASK                     0x0001
407*4882a593Smuzhiyun #define WM8350_LS_PROT_SHIFT                         0
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun /* Bit values for R199 (0xC7) */
410*4882a593Smuzhiyun #define WM8350_LS_ERRACT_NONE                       0
411*4882a593Smuzhiyun #define WM8350_LS_ERRACT_SHUTDOWN_CONV              1
412*4882a593Smuzhiyun #define WM8350_LS_ERRACT_SHUTDOWN_SYS               2
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun /*
415*4882a593Smuzhiyun  * R200 (0xC8) - LDO1 Control
416*4882a593Smuzhiyun  */
417*4882a593Smuzhiyun #define WM8350_LDO1_SWI                         0x4000
418*4882a593Smuzhiyun #define WM8350_LDO1_OPFLT                       0x0400
419*4882a593Smuzhiyun #define WM8350_LDO1_VSEL_MASK                   0x001F
420*4882a593Smuzhiyun #define WM8350_LDO1_VSEL_SHIFT                       0
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun /*
423*4882a593Smuzhiyun  * R201 (0xC9) - LDO1 Timeouts
424*4882a593Smuzhiyun  */
425*4882a593Smuzhiyun #define WM8350_LDO1_ERRACT_MASK                 0xC000
426*4882a593Smuzhiyun #define WM8350_LDO1_ERRACT_SHIFT                    14
427*4882a593Smuzhiyun #define WM8350_LDO1_ENSLOT_MASK                 0x3C00
428*4882a593Smuzhiyun #define WM8350_LDO1_ENSLOT_SHIFT                    10
429*4882a593Smuzhiyun #define WM8350_LDO1_SDSLOT_MASK                 0x03C0
430*4882a593Smuzhiyun #define WM8350_LDO1_UVTO_MASK                   0x0030
431*4882a593Smuzhiyun #define WM8350_LDO1_SDSLOT_SHIFT                     6
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun /* Bit values for R201 (0xC9) */
434*4882a593Smuzhiyun #define WM8350_LDO1_ERRACT_NONE                       0
435*4882a593Smuzhiyun #define WM8350_LDO1_ERRACT_SHUTDOWN_CONV              1
436*4882a593Smuzhiyun #define WM8350_LDO1_ERRACT_SHUTDOWN_SYS               2
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun /*
439*4882a593Smuzhiyun  * R202 (0xCA) - LDO1 Low Power
440*4882a593Smuzhiyun  */
441*4882a593Smuzhiyun #define WM8350_LDO1_HIB_MODE_MASK               0x3000
442*4882a593Smuzhiyun #define WM8350_LDO1_HIB_TRIG_MASK               0x0300
443*4882a593Smuzhiyun #define WM8350_LDO1_VIMG_MASK                   0x001F
444*4882a593Smuzhiyun #define WM8350_LDO1_HIB_MODE_DIS		(0x1 << 12)
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun /*
448*4882a593Smuzhiyun  * R203 (0xCB) - LDO2 Control
449*4882a593Smuzhiyun  */
450*4882a593Smuzhiyun #define WM8350_LDO2_SWI                         0x4000
451*4882a593Smuzhiyun #define WM8350_LDO2_OPFLT                       0x0400
452*4882a593Smuzhiyun #define WM8350_LDO2_VSEL_MASK                   0x001F
453*4882a593Smuzhiyun #define WM8350_LDO2_VSEL_SHIFT                       0
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun /*
456*4882a593Smuzhiyun  * R204 (0xCC) - LDO2 Timeouts
457*4882a593Smuzhiyun  */
458*4882a593Smuzhiyun #define WM8350_LDO2_ERRACT_MASK                 0xC000
459*4882a593Smuzhiyun #define WM8350_LDO2_ERRACT_SHIFT                    14
460*4882a593Smuzhiyun #define WM8350_LDO2_ENSLOT_MASK                 0x3C00
461*4882a593Smuzhiyun #define WM8350_LDO2_ENSLOT_SHIFT                    10
462*4882a593Smuzhiyun #define WM8350_LDO2_SDSLOT_MASK                 0x03C0
463*4882a593Smuzhiyun #define WM8350_LDO2_SDSLOT_SHIFT                     6
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun /* Bit values for R204 (0xCC) */
466*4882a593Smuzhiyun #define WM8350_LDO2_ERRACT_NONE                       0
467*4882a593Smuzhiyun #define WM8350_LDO2_ERRACT_SHUTDOWN_CONV              1
468*4882a593Smuzhiyun #define WM8350_LDO2_ERRACT_SHUTDOWN_SYS               2
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun /*
471*4882a593Smuzhiyun  * R205 (0xCD) - LDO2 Low Power
472*4882a593Smuzhiyun  */
473*4882a593Smuzhiyun #define WM8350_LDO2_HIB_MODE_MASK               0x3000
474*4882a593Smuzhiyun #define WM8350_LDO2_HIB_TRIG_MASK               0x0300
475*4882a593Smuzhiyun #define WM8350_LDO2_VIMG_MASK                   0x001F
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun /*
478*4882a593Smuzhiyun  * R206 (0xCE) - LDO3 Control
479*4882a593Smuzhiyun  */
480*4882a593Smuzhiyun #define WM8350_LDO3_SWI                         0x4000
481*4882a593Smuzhiyun #define WM8350_LDO3_OPFLT                       0x0400
482*4882a593Smuzhiyun #define WM8350_LDO3_VSEL_MASK                   0x001F
483*4882a593Smuzhiyun #define WM8350_LDO3_VSEL_SHIFT                       0
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun /*
486*4882a593Smuzhiyun  * R207 (0xCF) - LDO3 Timeouts
487*4882a593Smuzhiyun  */
488*4882a593Smuzhiyun #define WM8350_LDO3_ERRACT_MASK                 0xC000
489*4882a593Smuzhiyun #define WM8350_LDO3_ERRACT_SHIFT                    14
490*4882a593Smuzhiyun #define WM8350_LDO3_ENSLOT_MASK                 0x3C00
491*4882a593Smuzhiyun #define WM8350_LDO3_ENSLOT_SHIFT                    10
492*4882a593Smuzhiyun #define WM8350_LDO3_SDSLOT_MASK                 0x03C0
493*4882a593Smuzhiyun #define WM8350_LDO3_UVTO_MASK                   0x0030
494*4882a593Smuzhiyun #define WM8350_LDO3_SDSLOT_SHIFT                     6
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun /* Bit values for R207 (0xCF) */
497*4882a593Smuzhiyun #define WM8350_LDO3_ERRACT_NONE                       0
498*4882a593Smuzhiyun #define WM8350_LDO3_ERRACT_SHUTDOWN_CONV              1
499*4882a593Smuzhiyun #define WM8350_LDO3_ERRACT_SHUTDOWN_SYS               2
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun /*
502*4882a593Smuzhiyun  * R208 (0xD0) - LDO3 Low Power
503*4882a593Smuzhiyun  */
504*4882a593Smuzhiyun #define WM8350_LDO3_HIB_MODE_MASK               0x3000
505*4882a593Smuzhiyun #define WM8350_LDO3_HIB_TRIG_MASK               0x0300
506*4882a593Smuzhiyun #define WM8350_LDO3_VIMG_MASK                   0x001F
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun /*
509*4882a593Smuzhiyun  * R209 (0xD1) - LDO4 Control
510*4882a593Smuzhiyun  */
511*4882a593Smuzhiyun #define WM8350_LDO4_SWI                         0x4000
512*4882a593Smuzhiyun #define WM8350_LDO4_OPFLT                       0x0400
513*4882a593Smuzhiyun #define WM8350_LDO4_VSEL_MASK                   0x001F
514*4882a593Smuzhiyun #define WM8350_LDO4_VSEL_SHIFT                       0
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun /*
517*4882a593Smuzhiyun  * R210 (0xD2) - LDO4 Timeouts
518*4882a593Smuzhiyun  */
519*4882a593Smuzhiyun #define WM8350_LDO4_ERRACT_MASK                 0xC000
520*4882a593Smuzhiyun #define WM8350_LDO4_ERRACT_SHIFT                    14
521*4882a593Smuzhiyun #define WM8350_LDO4_ENSLOT_MASK                 0x3C00
522*4882a593Smuzhiyun #define WM8350_LDO4_ENSLOT_SHIFT                    10
523*4882a593Smuzhiyun #define WM8350_LDO4_SDSLOT_MASK                 0x03C0
524*4882a593Smuzhiyun #define WM8350_LDO4_UVTO_MASK                   0x0030
525*4882a593Smuzhiyun #define WM8350_LDO4_SDSLOT_SHIFT                     6
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun /* Bit values for R210 (0xD2) */
528*4882a593Smuzhiyun #define WM8350_LDO4_ERRACT_NONE                       0
529*4882a593Smuzhiyun #define WM8350_LDO4_ERRACT_SHUTDOWN_CONV              1
530*4882a593Smuzhiyun #define WM8350_LDO4_ERRACT_SHUTDOWN_SYS               2
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun /*
533*4882a593Smuzhiyun  * R211 (0xD3) - LDO4 Low Power
534*4882a593Smuzhiyun  */
535*4882a593Smuzhiyun #define WM8350_LDO4_HIB_MODE_MASK               0x3000
536*4882a593Smuzhiyun #define WM8350_LDO4_HIB_TRIG_MASK               0x0300
537*4882a593Smuzhiyun #define WM8350_LDO4_VIMG_MASK                   0x001F
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun /*
540*4882a593Smuzhiyun  * R215 (0xD7) - VCC_FAULT Masks
541*4882a593Smuzhiyun  */
542*4882a593Smuzhiyun #define WM8350_LS_FAULT                         0x8000
543*4882a593Smuzhiyun #define WM8350_LDO4_FAULT                       0x0800
544*4882a593Smuzhiyun #define WM8350_LDO3_FAULT                       0x0400
545*4882a593Smuzhiyun #define WM8350_LDO2_FAULT                       0x0200
546*4882a593Smuzhiyun #define WM8350_LDO1_FAULT                       0x0100
547*4882a593Smuzhiyun #define WM8350_DC6_FAULT                        0x0020
548*4882a593Smuzhiyun #define WM8350_DC5_FAULT                        0x0010
549*4882a593Smuzhiyun #define WM8350_DC4_FAULT                        0x0008
550*4882a593Smuzhiyun #define WM8350_DC3_FAULT                        0x0004
551*4882a593Smuzhiyun #define WM8350_DC2_FAULT                        0x0002
552*4882a593Smuzhiyun #define WM8350_DC1_FAULT                        0x0001
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun /*
555*4882a593Smuzhiyun  * R216 (0xD8) - Main Bandgap Control
556*4882a593Smuzhiyun  */
557*4882a593Smuzhiyun #define WM8350_MBG_LOAD_FUSES                   0x8000
558*4882a593Smuzhiyun #define WM8350_MBG_FUSE_WPREP                   0x4000
559*4882a593Smuzhiyun #define WM8350_MBG_FUSE_WRITE                   0x2000
560*4882a593Smuzhiyun #define WM8350_MBG_FUSE_TRIM_MASK               0x1F00
561*4882a593Smuzhiyun #define WM8350_MBG_TRIM_SRC                     0x0020
562*4882a593Smuzhiyun #define WM8350_MBG_USER_TRIM_MASK               0x001F
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun /*
565*4882a593Smuzhiyun  * R217 (0xD9) - OSC Control
566*4882a593Smuzhiyun  */
567*4882a593Smuzhiyun #define WM8350_OSC_LOAD_FUSES                   0x8000
568*4882a593Smuzhiyun #define WM8350_OSC_FUSE_WPREP                   0x4000
569*4882a593Smuzhiyun #define WM8350_OSC_FUSE_WRITE                   0x2000
570*4882a593Smuzhiyun #define WM8350_OSC_FUSE_TRIM_MASK               0x0F00
571*4882a593Smuzhiyun #define WM8350_OSC_TRIM_SRC                     0x0020
572*4882a593Smuzhiyun #define WM8350_OSC_USER_TRIM_MASK               0x000F
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun /*
575*4882a593Smuzhiyun  * R248 (0xF8) - DCDC1 Force PWM
576*4882a593Smuzhiyun  */
577*4882a593Smuzhiyun #define WM8350_DCDC1_FORCE_PWM_ENA              0x0010
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun /*
580*4882a593Smuzhiyun  * R250 (0xFA) - DCDC3 Force PWM
581*4882a593Smuzhiyun  */
582*4882a593Smuzhiyun #define WM8350_DCDC3_FORCE_PWM_ENA              0x0010
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun /*
585*4882a593Smuzhiyun  * R251 (0xFB) - DCDC4 Force PWM
586*4882a593Smuzhiyun  */
587*4882a593Smuzhiyun #define WM8350_DCDC4_FORCE_PWM_ENA              0x0010
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun /*
590*4882a593Smuzhiyun  * R253 (0xFD) - DCDC1 Force PWM
591*4882a593Smuzhiyun  */
592*4882a593Smuzhiyun #define WM8350_DCDC6_FORCE_PWM_ENA              0x0010
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun /*
595*4882a593Smuzhiyun  * DCDC's
596*4882a593Smuzhiyun  */
597*4882a593Smuzhiyun #define WM8350_DCDC_1				0
598*4882a593Smuzhiyun #define WM8350_DCDC_2				1
599*4882a593Smuzhiyun #define WM8350_DCDC_3				2
600*4882a593Smuzhiyun #define WM8350_DCDC_4				3
601*4882a593Smuzhiyun #define WM8350_DCDC_5				4
602*4882a593Smuzhiyun #define WM8350_DCDC_6				5
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun /* DCDC modes */
605*4882a593Smuzhiyun #define WM8350_DCDC_ACTIVE_STANDBY		0
606*4882a593Smuzhiyun #define WM8350_DCDC_ACTIVE_PULSE		1
607*4882a593Smuzhiyun #define WM8350_DCDC_SLEEP_NORMAL		0
608*4882a593Smuzhiyun #define WM8350_DCDC_SLEEP_LOW			1
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun /* DCDC Low power (Hibernate) mode */
611*4882a593Smuzhiyun #define WM8350_DCDC_HIB_MODE_CUR		(0 << 12)
612*4882a593Smuzhiyun #define WM8350_DCDC_HIB_MODE_IMAGE		(1 << 12)
613*4882a593Smuzhiyun #define WM8350_DCDC_HIB_MODE_STANDBY		(2 << 12)
614*4882a593Smuzhiyun #define WM8350_DCDC_HIB_MODE_LDO		(4 << 12)
615*4882a593Smuzhiyun #define WM8350_DCDC_HIB_MODE_LDO_IM		(5 << 12)
616*4882a593Smuzhiyun #define WM8350_DCDC_HIB_MODE_DIS		(7 << 12)
617*4882a593Smuzhiyun #define WM8350_DCDC_HIB_MODE_MASK		(7 << 12)
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun /* DCDC Low Power (Hibernate) signal */
620*4882a593Smuzhiyun #define WM8350_DCDC_HIB_SIG_REG			(0 << 8)
621*4882a593Smuzhiyun #define WM8350_DCDC_HIB_SIG_LPWR1		(1 << 8)
622*4882a593Smuzhiyun #define WM8350_DCDC_HIB_SIG_LPWR2		(2 << 8)
623*4882a593Smuzhiyun #define WM8350_DCDC_HIB_SIG_LPWR3		(3 << 8)
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun /* LDO Low power (Hibernate) mode */
626*4882a593Smuzhiyun #define WM8350_LDO_HIB_MODE_IMAGE		(0 << 0)
627*4882a593Smuzhiyun #define WM8350_LDO_HIB_MODE_DIS			(1 << 0)
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun /* LDO Low Power (Hibernate) signal */
630*4882a593Smuzhiyun #define WM8350_LDO_HIB_SIG_REG			(0 << 8)
631*4882a593Smuzhiyun #define WM8350_LDO_HIB_SIG_LPWR1		(1 << 8)
632*4882a593Smuzhiyun #define WM8350_LDO_HIB_SIG_LPWR2		(2 << 8)
633*4882a593Smuzhiyun #define WM8350_LDO_HIB_SIG_LPWR3		(3 << 8)
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun /*
636*4882a593Smuzhiyun  * LDOs
637*4882a593Smuzhiyun  */
638*4882a593Smuzhiyun #define WM8350_LDO_1				6
639*4882a593Smuzhiyun #define WM8350_LDO_2				7
640*4882a593Smuzhiyun #define WM8350_LDO_3				8
641*4882a593Smuzhiyun #define WM8350_LDO_4				9
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun /*
644*4882a593Smuzhiyun  * ISINKs
645*4882a593Smuzhiyun  */
646*4882a593Smuzhiyun #define WM8350_ISINK_A				10
647*4882a593Smuzhiyun #define WM8350_ISINK_B				11
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun #define WM8350_ISINK_MODE_BOOST			0
650*4882a593Smuzhiyun #define WM8350_ISINK_MODE_SWITCH		1
651*4882a593Smuzhiyun #define WM8350_ISINK_ILIM_NORMAL		0
652*4882a593Smuzhiyun #define WM8350_ISINK_ILIM_LOW			1
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_DISABLE		0
655*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_ENABLE		1
656*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_TRIG_BIT		0
657*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_TRIG_GPIO		1
658*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_MODE_EN		(1 << 13)
659*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_MODE_DIS		(0 << 13)
660*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_DUR_32MS		(0 << 8)
661*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_DUR_64MS		(1 << 8)
662*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_DUR_96MS		(2 << 8)
663*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_DUR_1024MS		(3 << 8)
664*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_ON_INSTANT		(0 << 0)
665*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_ON_0_25S		(1 << 0)
666*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_ON_0_50S		(2 << 0)
667*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_ON_1_00S		(3 << 0)
668*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_ON_1_95S		(1 << 0)
669*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_ON_3_91S		(2 << 0)
670*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_ON_7_80S		(3 << 0)
671*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_OFF_INSTANT		(0 << 4)
672*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_OFF_0_25S		(1 << 4)
673*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_OFF_0_50S		(2 << 4)
674*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_OFF_1_00S		(3 << 4)
675*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_OFF_1_95S		(1 << 4)
676*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_OFF_3_91S		(2 << 4)
677*4882a593Smuzhiyun #define WM8350_ISINK_FLASH_OFF_7_80S		(3 << 4)
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun /*
680*4882a593Smuzhiyun  * Regulator Interrupts.
681*4882a593Smuzhiyun  */
682*4882a593Smuzhiyun #define WM8350_IRQ_CS1				13
683*4882a593Smuzhiyun #define WM8350_IRQ_CS2				14
684*4882a593Smuzhiyun #define WM8350_IRQ_UV_LDO4			25
685*4882a593Smuzhiyun #define WM8350_IRQ_UV_LDO3			26
686*4882a593Smuzhiyun #define WM8350_IRQ_UV_LDO2			27
687*4882a593Smuzhiyun #define WM8350_IRQ_UV_LDO1			28
688*4882a593Smuzhiyun #define WM8350_IRQ_UV_DC6			29
689*4882a593Smuzhiyun #define WM8350_IRQ_UV_DC5			30
690*4882a593Smuzhiyun #define WM8350_IRQ_UV_DC4			31
691*4882a593Smuzhiyun #define WM8350_IRQ_UV_DC3			32
692*4882a593Smuzhiyun #define WM8350_IRQ_UV_DC2			33
693*4882a593Smuzhiyun #define WM8350_IRQ_UV_DC1			34
694*4882a593Smuzhiyun #define WM8350_IRQ_OC_LS			35
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun #define NUM_WM8350_REGULATORS			12
697*4882a593Smuzhiyun 
698*4882a593Smuzhiyun struct wm8350;
699*4882a593Smuzhiyun struct platform_device;
700*4882a593Smuzhiyun struct regulator_init_data;
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun /*
703*4882a593Smuzhiyun  * WM8350 LED platform data
704*4882a593Smuzhiyun  */
705*4882a593Smuzhiyun struct wm8350_led_platform_data {
706*4882a593Smuzhiyun 	const char *name;
707*4882a593Smuzhiyun 	const char *default_trigger;
708*4882a593Smuzhiyun 	int max_uA;
709*4882a593Smuzhiyun };
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun struct wm8350_led {
712*4882a593Smuzhiyun 	struct platform_device *pdev;
713*4882a593Smuzhiyun 	struct work_struct work;
714*4882a593Smuzhiyun 	spinlock_t value_lock;
715*4882a593Smuzhiyun 	enum led_brightness value;
716*4882a593Smuzhiyun 	struct led_classdev cdev;
717*4882a593Smuzhiyun 	int max_uA_index;
718*4882a593Smuzhiyun 	int enabled;
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	struct regulator *isink;
721*4882a593Smuzhiyun 	struct regulator_consumer_supply isink_consumer;
722*4882a593Smuzhiyun 	struct regulator_init_data isink_init;
723*4882a593Smuzhiyun 	struct regulator *dcdc;
724*4882a593Smuzhiyun 	struct regulator_consumer_supply dcdc_consumer;
725*4882a593Smuzhiyun 	struct regulator_init_data dcdc_init;
726*4882a593Smuzhiyun };
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun struct wm8350_pmic {
729*4882a593Smuzhiyun 	/* Number of regulators of each type on this device */
730*4882a593Smuzhiyun 	int max_dcdc;
731*4882a593Smuzhiyun 	int max_isink;
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	/* ISINK to DCDC mapping */
734*4882a593Smuzhiyun 	int isink_A_dcdc;
735*4882a593Smuzhiyun 	int isink_B_dcdc;
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	/* hibernate configs */
738*4882a593Smuzhiyun 	u16 dcdc1_hib_mode;
739*4882a593Smuzhiyun 	u16 dcdc3_hib_mode;
740*4882a593Smuzhiyun 	u16 dcdc4_hib_mode;
741*4882a593Smuzhiyun 	u16 dcdc6_hib_mode;
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	/* regulator devices */
744*4882a593Smuzhiyun 	struct platform_device *pdev[NUM_WM8350_REGULATORS];
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun 	/* LED devices */
747*4882a593Smuzhiyun 	struct wm8350_led led[2];
748*4882a593Smuzhiyun };
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
751*4882a593Smuzhiyun 			      struct regulator_init_data *initdata);
752*4882a593Smuzhiyun int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
753*4882a593Smuzhiyun 			struct wm8350_led_platform_data *pdata);
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun /*
756*4882a593Smuzhiyun  * Additional DCDC control not supported via regulator API
757*4882a593Smuzhiyun  */
758*4882a593Smuzhiyun int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
759*4882a593Smuzhiyun 			 u16 stop, u16 fault);
760*4882a593Smuzhiyun int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
761*4882a593Smuzhiyun 			   u16 ilim, u16 ramp, u16 feedback);
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun /*
764*4882a593Smuzhiyun  * Additional LDO control not supported via regulator API
765*4882a593Smuzhiyun  */
766*4882a593Smuzhiyun int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun /*
769*4882a593Smuzhiyun  * Additional ISINK control not supported via regulator API
770*4882a593Smuzhiyun  */
771*4882a593Smuzhiyun int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
772*4882a593Smuzhiyun 			   u16 trigger, u16 duration, u16 on_ramp,
773*4882a593Smuzhiyun 			   u16 off_ramp, u16 drive);
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun #endif
776