1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Marvell Armada AP807 Quad 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2019 Marvell Technology Group Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "armada-ap807.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Marvell Armada AP807 Quad"; 12*4882a593Smuzhiyun compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun cpus { 15*4882a593Smuzhiyun #address-cells = <1>; 16*4882a593Smuzhiyun #size-cells = <0>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun cpu0: cpu@0 { 19*4882a593Smuzhiyun device_type = "cpu"; 20*4882a593Smuzhiyun compatible = "arm,cortex-a72"; 21*4882a593Smuzhiyun reg = <0x000>; 22*4882a593Smuzhiyun enable-method = "psci"; 23*4882a593Smuzhiyun #cooling-cells = <2>; 24*4882a593Smuzhiyun clocks = <&cpu_clk 0>; 25*4882a593Smuzhiyun i-cache-size = <0xc000>; 26*4882a593Smuzhiyun i-cache-line-size = <64>; 27*4882a593Smuzhiyun i-cache-sets = <256>; 28*4882a593Smuzhiyun d-cache-size = <0x8000>; 29*4882a593Smuzhiyun d-cache-line-size = <64>; 30*4882a593Smuzhiyun d-cache-sets = <256>; 31*4882a593Smuzhiyun next-level-cache = <&l2_0>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun cpu1: cpu@1 { 34*4882a593Smuzhiyun device_type = "cpu"; 35*4882a593Smuzhiyun compatible = "arm,cortex-a72"; 36*4882a593Smuzhiyun reg = <0x001>; 37*4882a593Smuzhiyun enable-method = "psci"; 38*4882a593Smuzhiyun #cooling-cells = <2>; 39*4882a593Smuzhiyun clocks = <&cpu_clk 0>; 40*4882a593Smuzhiyun i-cache-size = <0xc000>; 41*4882a593Smuzhiyun i-cache-line-size = <64>; 42*4882a593Smuzhiyun i-cache-sets = <256>; 43*4882a593Smuzhiyun d-cache-size = <0x8000>; 44*4882a593Smuzhiyun d-cache-line-size = <64>; 45*4882a593Smuzhiyun d-cache-sets = <256>; 46*4882a593Smuzhiyun next-level-cache = <&l2_0>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun cpu2: cpu@100 { 49*4882a593Smuzhiyun device_type = "cpu"; 50*4882a593Smuzhiyun compatible = "arm,cortex-a72"; 51*4882a593Smuzhiyun reg = <0x100>; 52*4882a593Smuzhiyun enable-method = "psci"; 53*4882a593Smuzhiyun #cooling-cells = <2>; 54*4882a593Smuzhiyun clocks = <&cpu_clk 1>; 55*4882a593Smuzhiyun i-cache-size = <0xc000>; 56*4882a593Smuzhiyun i-cache-line-size = <64>; 57*4882a593Smuzhiyun i-cache-sets = <256>; 58*4882a593Smuzhiyun d-cache-size = <0x8000>; 59*4882a593Smuzhiyun d-cache-line-size = <64>; 60*4882a593Smuzhiyun d-cache-sets = <256>; 61*4882a593Smuzhiyun next-level-cache = <&l2_1>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun cpu3: cpu@101 { 64*4882a593Smuzhiyun device_type = "cpu"; 65*4882a593Smuzhiyun compatible = "arm,cortex-a72"; 66*4882a593Smuzhiyun reg = <0x101>; 67*4882a593Smuzhiyun enable-method = "psci"; 68*4882a593Smuzhiyun #cooling-cells = <2>; 69*4882a593Smuzhiyun clocks = <&cpu_clk 1>; 70*4882a593Smuzhiyun i-cache-size = <0xc000>; 71*4882a593Smuzhiyun i-cache-line-size = <64>; 72*4882a593Smuzhiyun i-cache-sets = <256>; 73*4882a593Smuzhiyun d-cache-size = <0x8000>; 74*4882a593Smuzhiyun d-cache-line-size = <64>; 75*4882a593Smuzhiyun d-cache-sets = <256>; 76*4882a593Smuzhiyun next-level-cache = <&l2_1>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun l2_0: l2-cache0 { 80*4882a593Smuzhiyun compatible = "cache"; 81*4882a593Smuzhiyun cache-size = <0x80000>; 82*4882a593Smuzhiyun cache-line-size = <64>; 83*4882a593Smuzhiyun cache-sets = <512>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun l2_1: l2-cache1 { 87*4882a593Smuzhiyun compatible = "cache"; 88*4882a593Smuzhiyun cache-size = <0x80000>; 89*4882a593Smuzhiyun cache-line-size = <64>; 90*4882a593Smuzhiyun cache-sets = <512>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun}; 94