1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MPC8272 ADS Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2005,2008 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "MPC8272ADS"; 12*4882a593Smuzhiyun compatible = "fsl,mpc8272ads"; 13*4882a593Smuzhiyun #address-cells = <1>; 14*4882a593Smuzhiyun #size-cells = <1>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun ethernet0 = ð0; 18*4882a593Smuzhiyun ethernet1 = ð1; 19*4882a593Smuzhiyun serial0 = &scc1; 20*4882a593Smuzhiyun serial1 = &scc4; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun cpus { 24*4882a593Smuzhiyun #address-cells = <1>; 25*4882a593Smuzhiyun #size-cells = <0>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun PowerPC,8272@0 { 28*4882a593Smuzhiyun device_type = "cpu"; 29*4882a593Smuzhiyun reg = <0x0>; 30*4882a593Smuzhiyun d-cache-line-size = <32>; 31*4882a593Smuzhiyun i-cache-line-size = <32>; 32*4882a593Smuzhiyun d-cache-size = <16384>; 33*4882a593Smuzhiyun i-cache-size = <16384>; 34*4882a593Smuzhiyun timebase-frequency = <0>; 35*4882a593Smuzhiyun bus-frequency = <0>; 36*4882a593Smuzhiyun clock-frequency = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun memory { 41*4882a593Smuzhiyun device_type = "memory"; 42*4882a593Smuzhiyun reg = <0x0 0x0>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun localbus@f0010100 { 46*4882a593Smuzhiyun compatible = "fsl,mpc8272-localbus", 47*4882a593Smuzhiyun "fsl,pq2-localbus"; 48*4882a593Smuzhiyun #address-cells = <2>; 49*4882a593Smuzhiyun #size-cells = <1>; 50*4882a593Smuzhiyun reg = <0xf0010100 0x40>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ranges = <0x0 0x0 0xff800000 0x00800000 53*4882a593Smuzhiyun 0x1 0x0 0xf4500000 0x8000 54*4882a593Smuzhiyun 0x3 0x0 0xf8200000 0x8000>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun flash@0,0 { 57*4882a593Smuzhiyun compatible = "jedec-flash"; 58*4882a593Smuzhiyun reg = <0x0 0x0 0x00800000>; 59*4882a593Smuzhiyun bank-width = <4>; 60*4882a593Smuzhiyun device-width = <1>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun board-control@1,0 { 64*4882a593Smuzhiyun reg = <0x1 0x0 0x20>; 65*4882a593Smuzhiyun compatible = "fsl,mpc8272ads-bcsr"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun PCI_PIC: interrupt-controller@3,0 { 69*4882a593Smuzhiyun compatible = "fsl,mpc8272ads-pci-pic", 70*4882a593Smuzhiyun "fsl,pq2ads-pci-pic"; 71*4882a593Smuzhiyun #interrupt-cells = <1>; 72*4882a593Smuzhiyun interrupt-controller; 73*4882a593Smuzhiyun reg = <0x3 0x0 0x8>; 74*4882a593Smuzhiyun interrupt-parent = <&PIC>; 75*4882a593Smuzhiyun interrupts = <20 8>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun pci@f0010800 { 81*4882a593Smuzhiyun device_type = "pci"; 82*4882a593Smuzhiyun reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; 83*4882a593Smuzhiyun compatible = "fsl,mpc8272-pci", "fsl,pq2-pci"; 84*4882a593Smuzhiyun #interrupt-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <2>; 86*4882a593Smuzhiyun #address-cells = <3>; 87*4882a593Smuzhiyun clock-frequency = <66666666>; 88*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 89*4882a593Smuzhiyun interrupt-map = < 90*4882a593Smuzhiyun /* IDSEL 0x16 */ 91*4882a593Smuzhiyun 0xb000 0x0 0x0 0x1 &PCI_PIC 0 92*4882a593Smuzhiyun 0xb000 0x0 0x0 0x2 &PCI_PIC 1 93*4882a593Smuzhiyun 0xb000 0x0 0x0 0x3 &PCI_PIC 2 94*4882a593Smuzhiyun 0xb000 0x0 0x0 0x4 &PCI_PIC 3 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* IDSEL 0x17 */ 97*4882a593Smuzhiyun 0xb800 0x0 0x0 0x1 &PCI_PIC 4 98*4882a593Smuzhiyun 0xb800 0x0 0x0 0x2 &PCI_PIC 5 99*4882a593Smuzhiyun 0xb800 0x0 0x0 0x3 &PCI_PIC 6 100*4882a593Smuzhiyun 0xb800 0x0 0x0 0x4 &PCI_PIC 7 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* IDSEL 0x18 */ 103*4882a593Smuzhiyun 0xc000 0x0 0x0 0x1 &PCI_PIC 8 104*4882a593Smuzhiyun 0xc000 0x0 0x0 0x2 &PCI_PIC 9 105*4882a593Smuzhiyun 0xc000 0x0 0x0 0x3 &PCI_PIC 10 106*4882a593Smuzhiyun 0xc000 0x0 0x0 0x4 &PCI_PIC 11>; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun interrupt-parent = <&PIC>; 109*4882a593Smuzhiyun interrupts = <18 8>; 110*4882a593Smuzhiyun ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 111*4882a593Smuzhiyun 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 112*4882a593Smuzhiyun 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun soc@f0000000 { 116*4882a593Smuzhiyun #address-cells = <1>; 117*4882a593Smuzhiyun #size-cells = <1>; 118*4882a593Smuzhiyun device_type = "soc"; 119*4882a593Smuzhiyun compatible = "fsl,mpc8272", "fsl,pq2-soc"; 120*4882a593Smuzhiyun ranges = <0x0 0xf0000000 0x53000>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun // Temporary -- will go away once kernel uses ranges for get_immrbase(). 123*4882a593Smuzhiyun reg = <0xf0000000 0x53000>; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun cpm@119c0 { 126*4882a593Smuzhiyun #address-cells = <1>; 127*4882a593Smuzhiyun #size-cells = <1>; 128*4882a593Smuzhiyun compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; 129*4882a593Smuzhiyun reg = <0x119c0 0x30>; 130*4882a593Smuzhiyun ranges; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun muram@0 { 133*4882a593Smuzhiyun #address-cells = <1>; 134*4882a593Smuzhiyun #size-cells = <1>; 135*4882a593Smuzhiyun ranges = <0x0 0x0 0x10000>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun data@0 { 138*4882a593Smuzhiyun compatible = "fsl,cpm-muram-data"; 139*4882a593Smuzhiyun reg = <0x0 0x2000 0x9800 0x800>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun brg@119f0 { 144*4882a593Smuzhiyun compatible = "fsl,mpc8272-brg", 145*4882a593Smuzhiyun "fsl,cpm2-brg", 146*4882a593Smuzhiyun "fsl,cpm-brg"; 147*4882a593Smuzhiyun reg = <0x119f0 0x10 0x115f0 0x10>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun scc1: serial@11a00 { 151*4882a593Smuzhiyun device_type = "serial"; 152*4882a593Smuzhiyun compatible = "fsl,mpc8272-scc-uart", 153*4882a593Smuzhiyun "fsl,cpm2-scc-uart"; 154*4882a593Smuzhiyun reg = <0x11a00 0x20 0x8000 0x100>; 155*4882a593Smuzhiyun interrupts = <40 8>; 156*4882a593Smuzhiyun interrupt-parent = <&PIC>; 157*4882a593Smuzhiyun fsl,cpm-brg = <1>; 158*4882a593Smuzhiyun fsl,cpm-command = <0x800000>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun scc4: serial@11a60 { 162*4882a593Smuzhiyun device_type = "serial"; 163*4882a593Smuzhiyun compatible = "fsl,mpc8272-scc-uart", 164*4882a593Smuzhiyun "fsl,cpm2-scc-uart"; 165*4882a593Smuzhiyun reg = <0x11a60 0x20 0x8300 0x100>; 166*4882a593Smuzhiyun interrupts = <43 8>; 167*4882a593Smuzhiyun interrupt-parent = <&PIC>; 168*4882a593Smuzhiyun fsl,cpm-brg = <4>; 169*4882a593Smuzhiyun fsl,cpm-command = <0xce00000>; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun usb@11b60 { 173*4882a593Smuzhiyun compatible = "fsl,mpc8272-cpm-usb"; 174*4882a593Smuzhiyun reg = <0x11b60 0x40 0x8b00 0x100>; 175*4882a593Smuzhiyun interrupts = <11 8>; 176*4882a593Smuzhiyun interrupt-parent = <&PIC>; 177*4882a593Smuzhiyun mode = "peripheral"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun mdio@10d40 { 181*4882a593Smuzhiyun compatible = "fsl,mpc8272ads-mdio-bitbang", 182*4882a593Smuzhiyun "fsl,mpc8272-mdio-bitbang", 183*4882a593Smuzhiyun "fsl,cpm2-mdio-bitbang"; 184*4882a593Smuzhiyun reg = <0x10d40 0x14>; 185*4882a593Smuzhiyun #address-cells = <1>; 186*4882a593Smuzhiyun #size-cells = <0>; 187*4882a593Smuzhiyun fsl,mdio-pin = <18>; 188*4882a593Smuzhiyun fsl,mdc-pin = <19>; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun PHY0: ethernet-phy@0 { 191*4882a593Smuzhiyun interrupt-parent = <&PIC>; 192*4882a593Smuzhiyun interrupts = <23 8>; 193*4882a593Smuzhiyun reg = <0x0>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun PHY1: ethernet-phy@1 { 197*4882a593Smuzhiyun interrupt-parent = <&PIC>; 198*4882a593Smuzhiyun interrupts = <23 8>; 199*4882a593Smuzhiyun reg = <0x3>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun eth0: ethernet@11300 { 204*4882a593Smuzhiyun device_type = "network"; 205*4882a593Smuzhiyun compatible = "fsl,mpc8272-fcc-enet", 206*4882a593Smuzhiyun "fsl,cpm2-fcc-enet"; 207*4882a593Smuzhiyun reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>; 208*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 209*4882a593Smuzhiyun interrupts = <32 8>; 210*4882a593Smuzhiyun interrupt-parent = <&PIC>; 211*4882a593Smuzhiyun phy-handle = <&PHY0>; 212*4882a593Smuzhiyun linux,network-index = <0>; 213*4882a593Smuzhiyun fsl,cpm-command = <0x12000300>; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun eth1: ethernet@11320 { 217*4882a593Smuzhiyun device_type = "network"; 218*4882a593Smuzhiyun compatible = "fsl,mpc8272-fcc-enet", 219*4882a593Smuzhiyun "fsl,cpm2-fcc-enet"; 220*4882a593Smuzhiyun reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>; 221*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 222*4882a593Smuzhiyun interrupts = <33 8>; 223*4882a593Smuzhiyun interrupt-parent = <&PIC>; 224*4882a593Smuzhiyun phy-handle = <&PHY1>; 225*4882a593Smuzhiyun linux,network-index = <1>; 226*4882a593Smuzhiyun fsl,cpm-command = <0x16200300>; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun i2c@11860 { 230*4882a593Smuzhiyun compatible = "fsl,mpc8272-i2c", 231*4882a593Smuzhiyun "fsl,cpm2-i2c"; 232*4882a593Smuzhiyun reg = <0x11860 0x20 0x8afc 0x2>; 233*4882a593Smuzhiyun interrupts = <1 8>; 234*4882a593Smuzhiyun interrupt-parent = <&PIC>; 235*4882a593Smuzhiyun fsl,cpm-command = <0x29600000>; 236*4882a593Smuzhiyun #address-cells = <1>; 237*4882a593Smuzhiyun #size-cells = <0>; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun PIC: interrupt-controller@10c00 { 242*4882a593Smuzhiyun #interrupt-cells = <2>; 243*4882a593Smuzhiyun interrupt-controller; 244*4882a593Smuzhiyun reg = <0x10c00 0x80>; 245*4882a593Smuzhiyun compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic"; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun crypto@30000 { 249*4882a593Smuzhiyun compatible = "fsl,sec1.0"; 250*4882a593Smuzhiyun reg = <0x40000 0x13000>; 251*4882a593Smuzhiyun interrupts = <47 0x8>; 252*4882a593Smuzhiyun interrupt-parent = <&PIC>; 253*4882a593Smuzhiyun fsl,num-channels = <4>; 254*4882a593Smuzhiyun fsl,channel-fifo-len = <24>; 255*4882a593Smuzhiyun fsl,exec-units-mask = <0x7e>; 256*4882a593Smuzhiyun fsl,descriptor-types-mask = <0x1010415>; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun chosen { 261*4882a593Smuzhiyun stdout-path = "/soc/cpm/serial@11a00"; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun}; 264