13 #define SMI_HDR		((0x8 | 0x1) << 12)
14 #define SMI_BUSY_MASK	(0x8000)
15 #define SMIRD_OP	(0x2 << 10)
16 #define SMIWR_OP	(0x1 << 10)
17 #define SMI_MASK	0x1f
20 #define COMMAND_REG	0
24 #define GLOBAL		0x1b
26 #define GLOBAL_STATUS	0x00
27 #define PPU_STATE	0x8000
29 #define GLOBAL_CTRL	0x04
30 #define SW_RESET	0x8000
31 #define PPU_ENABLE	0x4000
43 		if (ret < 0) {  in sw_wait_rdy()
48 		if (timeout-- == 0) {  in sw_wait_rdy()
54 	return 0;  in sw_wait_rdy()
109 	return 0;  in sw_reg_write()
114 	int i, ret = 0;  in ppu_enable()
131 	for (i = 0; i < 1000; i++) {  in ppu_enable()
134 		if ((reg & 0xc000) == 0xc000)  in ppu_enable()
135 			return 0;  in ppu_enable()
144 	int i, ret = 0;  in ppu_disable()
161 	for (i = 0; i < 1000; i++) {  in ppu_disable()
164 		if ((reg & 0xc000) != 0xc000)  in ppu_disable()
165 			return 0;  in ppu_disable()
175 	int i, ret = 0;  in mv88e_sw_program()
184 	for (i = 0; i < regs_nb; i++) {  in mv88e_sw_program()
201 	return 0;  in mv88e_sw_program()
206 	int i, ret = 0;  in mv88e_sw_reset()
215 	reg = SW_RESET | PPU_ENABLE | 0x0400;  in mv88e_sw_reset()
223 	for (i = 0; i < 1000; i++) {  in mv88e_sw_reset()
226 		if ((reg & 0xc800) != 0xc800)  in mv88e_sw_reset()
227 			return 0;  in mv88e_sw_reset()
236 	u16 value = 0, phyaddr, reg, port;  in do_mvsw_reg_read()
251 	u16 value = 0, phyaddr, reg, port;  in do_mvsw_reg_write()
277 	if (strcmp(cmd, "read") == 0) {  in do_mvsw_reg()
284 	} else if (strcmp(cmd, "write") == 0) {  in do_mvsw_reg()