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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h13 #define REGS_AHB0_BASE 0x01C00000
14 #define REGS_AHB1_BASE 0x00800000
15 #define REGS_AHB2_BASE 0x03000000
16 #define REGS_APB0_BASE 0x06000000
17 #define REGS_APB1_BASE 0x07000000
18 #define REGS_RCPUS_BASE 0x08000000
20 #define SUNXI_SRAM_D_BASE 0x08100000
23 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
24 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
26 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/OK3568_Linux_fs/kernel/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_a38x_mc_static.h17 {0x1400, 0x7b00cc30, 0xffffffff},
18 {0x1404, 0x36301820, 0xffffffff},
19 {0x1408, 0x5415baab, 0xffffffff},
20 {0x140c, 0x38411def, 0xffffffff},
21 {0x1410, 0x18300000, 0xffffffff},
22 {0x1414, 0x00000700, 0xffffffff},
23 {0x1424, 0x0060f3ff, 0xffffffff},
24 {0x1428, 0x0011a940, 0xffffffff},
25 {0x142c, 0x28c5134, 0xffffffff},
26 {0x1474, 0x00000000, 0xffffffff},
[all …]
/OK3568_Linux_fs/kernel/arch/sparc/include/asm/
H A Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dstm32mp153.dtsi28 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
35 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
41 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
48 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
35 #clock-cells = <0>;
39 reg = <0x0d50>;
44 #clock-cells = <0>;
48 reg = <0x0b00>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
[all …]
H A Ddm816x-clocks.dtsi7 reg = <0x400 0x40>;
23 reg = <0x440 0x30>;
35 reg = <0x470 0x30>;
46 reg = <0x4a0 0x30>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
83 /* 0x48180000 */
86 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dcontregs.h15 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
16 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
17 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
18 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
19 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
20 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
21 #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
22 #define AC_SYNC_ERR 0x60000000 /* c fault type */
23 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
24 #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c59 printf("\n write reg 0x%08x = 0x%08x", addr, val); in dfs_reg_write()
77 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
118 u32 cs = 0; in ddr3_dfs_high_2_low()
124 freq_par = ddr3_get_freq_parameter(freq, 0); in ddr3_dfs_high_2_low()
134 /* [0] - DfsDllNextState - Disable */ in ddr3_dfs_high_2_low()
136 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
143 /* [0] - RetryMask - Disable */ in ddr3_dfs_high_2_low()
145 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
151 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
159 reg = (0x9 & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_high_2_low()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-qcom-hw.txt40 phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
51 #size-cells = <0>;
53 CPU0: cpu@0 {
56 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
72 reg = <0x0 0x100>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
85 reg = <0x0 0x200>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0x0 0x300>;
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/serial/
H A Dxr_usb_serial_hal.c20 #define XR_SET_MAP_XR21B142X 0
21 #define XR_GET_MAP_XR21B142X 0
23 #define XR_SET_MAP_XR21V141X 0
26 #define XR_SET_MAP_XR21B1411 0
33 int channel = 0; in xr_usb_serial_set_reg()
34 …//dev_info(&xr_usb_serial->control->dev, "%s Channel:%d 0x%02x = 0x%02x\n", __func__,channel,regnu… in xr_usb_serial_set_reg()
35 if((xr_usb_serial->DeviceProduct&0xfff0) == 0x1400) in xr_usb_serial_set_reg()
39 usb_sndctrlpipe(xr_usb_serial->dev, 0), /* endpoint pipe */ in xr_usb_serial_set_reg()
45 0, /* size */ in xr_usb_serial_set_reg()
48 else if((xr_usb_serial->DeviceProduct == 0x1410) || in xr_usb_serial_set_reg()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi12 #clock-cells = <0>;
20 #clock-cells = <0>;
29 #clock-cells = <0>;
32 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
38 #clock-cells = <0>;
42 reg = <0x0d50>;
47 #clock-cells = <0>;
51 reg = <0x0b00>;
55 #clock-cells = <0>;
63 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/x86/include/asm/arch-broadwell/
H A Diomap.h12 #define MCFG_BASE_ADDRESS 0xf0000000
13 #define MCFG_BASE_SIZE 0x4000000
15 #define HPET_BASE_ADDRESS 0xfed00000
17 #define MCH_BASE_ADDRESS 0xfed10000
18 #define MCH_BASE_SIZE 0x8000
20 #define DMI_BASE_ADDRESS 0xfed18000
21 #define DMI_BASE_SIZE 0x1000
23 #define EP_BASE_ADDRESS 0xfed19000
24 #define EP_BASE_SIZE 0x1000
26 #define EDRAM_BASE_ADDRESS 0xfed80000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-sdram-controller.txt20 reg = <0x1400 0x500>;
/OK3568_Linux_fs/kernel/arch/s390/include/asm/
H A Dlowcore.h21 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
22 __u32 ipl_parmblock_ptr; /* 0x0014 */
23 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
24 __u32 ext_params; /* 0x0080 */
25 __u16 ext_cpu_addr; /* 0x0084 */
26 __u16 ext_int_code; /* 0x0086 */
27 __u16 svc_ilc; /* 0x0088 */
28 __u16 svc_code; /* 0x008a */
29 __u16 pgm_ilc; /* 0x008c */
30 __u16 pgm_code; /* 0x008e */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dhardware_ti814x.h17 #define UART0_BASE 0x48020000
20 #define WDT_BASE 0x481C7000
23 #define CTRL_BASE 0x48140000
24 #define CTRL_DEVICE_BASE 0x48140600
27 #define PRCM_BASE 0x48180000
28 #define CM_PER 0x44E00000
29 #define CM_WKUP 0x44E00400
31 #define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
35 #define PLL_SUBSYS_BASE 0x481C5000
38 #define VTP0_CTRL_ADDR 0x48140E0C
[all …]
H A Dhardware_am33xx.h17 #define UART0_BASE 0x44E09000
20 #define GPIO2_BASE 0x481AC000
23 #define WDT_BASE 0x44E35000
26 #define CTRL_BASE 0x44E10000
27 #define CTRL_DEVICE_BASE 0x44E10600
30 #define PRCM_BASE 0x44E00000
31 #define CM_PER 0x44E00000
32 #define CM_WKUP 0x44E00400
33 #define CM_DPLL 0x44E00500
34 #define CM_RTC 0x44E00800
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Domap34xx.h17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
H A Dcm81xx.h21 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
22 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
23 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
24 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
27 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
28 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
29 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
32 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
33 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
34 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-ld11.c15 #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
16 #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
17 #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */
18 #define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
19 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */
22 #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
23 #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
30 uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); in uniphier_ld11_pll_init()
44 writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */ in uniphier_ld11_pll_init()
H A Dpll-ld20.c15 #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
16 #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
17 #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
18 #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
19 #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
20 #define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
21 #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
22 #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
23 #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
26 #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/intersil/prism54/
H A Dislpci_eth.h13 __le16 unk0; /* = 0x0000 */
14 __le16 length; /* = 0x1400 */
34 #define P80211CAPTURE_VERSION 0x80211001
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interconnect/
H A Dqcom,osm-l3.yaml54 #define RPMH_CXO_CLK 0
58 reg = <0x17d41000 0x1400>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Dpar_io.txt18 #size-cells = <0>;
41 reg = <0x1400 0x18>;
49 reg = <0x1460 0x18>;
/OK3568_Linux_fs/kernel/drivers/regulator/
H A Dqcom_spmi-regulator.c24 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
32 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]

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