1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Socionext Inc.
3*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "../init.h"
11*4882a593Smuzhiyun #include "../sc64-regs.h"
12*4882a593Smuzhiyun #include "pll.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* PLL type: SSC */
15*4882a593Smuzhiyun #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
16*4882a593Smuzhiyun #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
17*4882a593Smuzhiyun #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
18*4882a593Smuzhiyun #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
19*4882a593Smuzhiyun #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
20*4882a593Smuzhiyun #define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
21*4882a593Smuzhiyun #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
22*4882a593Smuzhiyun #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
23*4882a593Smuzhiyun #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* PLL type: VPLL27 */
26*4882a593Smuzhiyun #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
27*4882a593Smuzhiyun #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* PLL type: DSPLL */
30*4882a593Smuzhiyun #define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
31*4882a593Smuzhiyun #define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
32*4882a593Smuzhiyun
uniphier_ld20_pll_init(void)33*4882a593Smuzhiyun void uniphier_ld20_pll_init(void)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
36*4882a593Smuzhiyun /* do nothing for SPLL */
37*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
38*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
39*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
40*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun mdelay(1);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
45*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
46*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
47*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
48*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
49*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
50*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
51*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
54*4882a593Smuzhiyun uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
57*4882a593Smuzhiyun uniphier_ld20_dspll_init(SC_A2PLLCTRL);
58*4882a593Smuzhiyun }
59