1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * hardware_ti814x.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * TI814x hardware specific header 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __AM33XX_HARDWARE_TI814X_H 12*4882a593Smuzhiyun #define __AM33XX_HARDWARE_TI814X_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Module base addresses */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* UART Base Address */ 17*4882a593Smuzhiyun #define UART0_BASE 0x48020000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Watchdog Timer */ 20*4882a593Smuzhiyun #define WDT_BASE 0x481C7000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Control Module Base Address */ 23*4882a593Smuzhiyun #define CTRL_BASE 0x48140000 24*4882a593Smuzhiyun #define CTRL_DEVICE_BASE 0x48140600 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* PRCM Base Address */ 27*4882a593Smuzhiyun #define PRCM_BASE 0x48180000 28*4882a593Smuzhiyun #define CM_PER 0x44E00000 29*4882a593Smuzhiyun #define CM_WKUP 0x44E00400 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 32*4882a593Smuzhiyun #define PRM_RSTST (PRM_RSTCTRL + 8) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* PLL Subsystem Base Address */ 35*4882a593Smuzhiyun #define PLL_SUBSYS_BASE 0x481C5000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* VTP Base address */ 38*4882a593Smuzhiyun #define VTP0_CTRL_ADDR 0x48140E0C 39*4882a593Smuzhiyun #define VTP1_CTRL_ADDR 0x48140E10 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* DDR Base address */ 42*4882a593Smuzhiyun #define DDR_PHY_CMD_ADDR 0x47C0C400 43*4882a593Smuzhiyun #define DDR_PHY_DATA_ADDR 0x47C0C4C8 44*4882a593Smuzhiyun #define DDR_PHY_CMD_ADDR2 0x47C0C800 45*4882a593Smuzhiyun #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 46*4882a593Smuzhiyun #define DDR_DATA_REGS_NR 4 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) 49*4882a593Smuzhiyun #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* CPSW Config space */ 52*4882a593Smuzhiyun #define CPSW_MDIO_BASE 0x4A100800 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* RTC base address */ 55*4882a593Smuzhiyun #define RTC_BASE 0x480C0000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* OTG */ 58*4882a593Smuzhiyun #define USB0_OTG_BASE 0x47401000 59*4882a593Smuzhiyun #define USB1_OTG_BASE 0x47401800 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* __AM33XX_HARDWARE_TI814X_H */ 62