1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Socionext Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "../init.h"
11*4882a593Smuzhiyun #include "../sc64-regs.h"
12*4882a593Smuzhiyun #include "pll.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* PLL type: SSC */
15*4882a593Smuzhiyun #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
16*4882a593Smuzhiyun #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
17*4882a593Smuzhiyun #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */
18*4882a593Smuzhiyun #define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
19*4882a593Smuzhiyun #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* PLL type: VPLL27 */
22*4882a593Smuzhiyun #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
23*4882a593Smuzhiyun #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
24*4882a593Smuzhiyun
uniphier_ld11_pll_init(void)25*4882a593Smuzhiyun void uniphier_ld11_pll_init(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */
28*4882a593Smuzhiyun /* do nothing for SPLL */
29*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */
30*4882a593Smuzhiyun uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun mdelay(1);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
37*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
38*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
39*4882a593Smuzhiyun uniphier_ld20_sscpll_ssc_en(SC_DPLLCTRL);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
42*4882a593Smuzhiyun uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */
45*4882a593Smuzhiyun writel(SC_CA_GEARUPD, SC_CA53_GEARUPD);
46*4882a593Smuzhiyun }
47