1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> 3*4882a593Smuzhiyun * (C) Copyright 2007-2013 4*4882a593Smuzhiyun * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5*4882a593Smuzhiyun * Jerry Wang <wangflord@allwinnertech.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _SUNXI_CPU_SUN9I_H 11*4882a593Smuzhiyun #define _SUNXI_CPU_SUN9I_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define REGS_AHB0_BASE 0x01C00000 14*4882a593Smuzhiyun #define REGS_AHB1_BASE 0x00800000 15*4882a593Smuzhiyun #define REGS_AHB2_BASE 0x03000000 16*4882a593Smuzhiyun #define REGS_APB0_BASE 0x06000000 17*4882a593Smuzhiyun #define REGS_APB1_BASE 0x07000000 18*4882a593Smuzhiyun #define REGS_RCPUS_BASE 0x08000000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SUNXI_SRAM_D_BASE 0x08100000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* AHB0 Module */ 23*4882a593Smuzhiyun #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) 24*4882a593Smuzhiyun #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) 27*4882a593Smuzhiyun /* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ 28*4882a593Smuzhiyun #define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) 31*4882a593Smuzhiyun #define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) 32*4882a593Smuzhiyun #define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) 33*4882a593Smuzhiyun #define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) 34*4882a593Smuzhiyun #define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) 37*4882a593Smuzhiyun #define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) 38*4882a593Smuzhiyun #define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) 39*4882a593Smuzhiyun #define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) 42*4882a593Smuzhiyun #define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) 43*4882a593Smuzhiyun #define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) 46*4882a593Smuzhiyun #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) 47*4882a593Smuzhiyun #define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000) 48*4882a593Smuzhiyun #define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) 49*4882a593Smuzhiyun #define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* AHB1 Module */ 52*4882a593Smuzhiyun #define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) 53*4882a593Smuzhiyun #define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) 54*4882a593Smuzhiyun #define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) 55*4882a593Smuzhiyun #define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) 56*4882a593Smuzhiyun #define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* AHB2 Module */ 59*4882a593Smuzhiyun #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) 60*4882a593Smuzhiyun #define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) 61*4882a593Smuzhiyun #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) 62*4882a593Smuzhiyun #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) 63*4882a593Smuzhiyun #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) 66*4882a593Smuzhiyun #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) 67*4882a593Smuzhiyun #define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) 70*4882a593Smuzhiyun #define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) 71*4882a593Smuzhiyun #define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) 72*4882a593Smuzhiyun #define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) 75*4882a593Smuzhiyun #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) 76*4882a593Smuzhiyun #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) 77*4882a593Smuzhiyun #define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) 78*4882a593Smuzhiyun /* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ 79*4882a593Smuzhiyun #define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) 80*4882a593Smuzhiyun #define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* APB0 Module */ 83*4882a593Smuzhiyun #define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) 84*4882a593Smuzhiyun #define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) 85*4882a593Smuzhiyun #define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) 86*4882a593Smuzhiyun #define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) 87*4882a593Smuzhiyun #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) 88*4882a593Smuzhiyun #define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* APB1 Module */ 91*4882a593Smuzhiyun #define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) 92*4882a593Smuzhiyun #define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) 93*4882a593Smuzhiyun #define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) 94*4882a593Smuzhiyun #define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) 95*4882a593Smuzhiyun #define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) 96*4882a593Smuzhiyun #define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) 97*4882a593Smuzhiyun #define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) 98*4882a593Smuzhiyun #define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) 99*4882a593Smuzhiyun #define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) 100*4882a593Smuzhiyun #define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) 101*4882a593Smuzhiyun #define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* RCPUS Module */ 104*4882a593Smuzhiyun #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) 105*4882a593Smuzhiyun #define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) 106*4882a593Smuzhiyun #define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) 107*4882a593Smuzhiyun #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* Misc. */ 110*4882a593Smuzhiyun #define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ 111*4882a593Smuzhiyun #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 114*4882a593Smuzhiyun void sunxi_board_init(void); 115*4882a593Smuzhiyun void sunxi_reset(void); 116*4882a593Smuzhiyun int sunxi_get_sid(unsigned int *sid); 117*4882a593Smuzhiyun #endif 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #endif /* _SUNXI_CPU_SUN9I_H */ 120