1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Sibi Sankar <sibis@codeaurora.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. 14*4882a593Smuzhiyun The OSM L3 interconnect provider aggregates the L3 bandwidth requests 15*4882a593Smuzhiyun from CPU/GPU and relays it to the OSM. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun enum: 20*4882a593Smuzhiyun - qcom,sc7180-osm-l3 21*4882a593Smuzhiyun - qcom,sdm845-osm-l3 22*4882a593Smuzhiyun - qcom,sm8150-osm-l3 23*4882a593Smuzhiyun - qcom,sm8250-epss-l3 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clocks: 29*4882a593Smuzhiyun items: 30*4882a593Smuzhiyun - description: xo clock 31*4882a593Smuzhiyun - description: alternate clock 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clock-names: 34*4882a593Smuzhiyun items: 35*4882a593Smuzhiyun - const: xo 36*4882a593Smuzhiyun - const: alternate 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun '#interconnect-cells': 39*4882a593Smuzhiyun const: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunrequired: 42*4882a593Smuzhiyun - compatible 43*4882a593Smuzhiyun - reg 44*4882a593Smuzhiyun - clocks 45*4882a593Smuzhiyun - clock-names 46*4882a593Smuzhiyun - '#interconnect-cells' 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunadditionalProperties: false 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunexamples: 51*4882a593Smuzhiyun - | 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define GPLL0 165 54*4882a593Smuzhiyun #define RPMH_CXO_CLK 0 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun osm_l3: interconnect@17d41000 { 57*4882a593Smuzhiyun compatible = "qcom,sdm845-osm-l3"; 58*4882a593Smuzhiyun reg = <0x17d41000 0x1400>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 61*4882a593Smuzhiyun clock-names = "xo", "alternate"; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #interconnect-cells = <1>; 64*4882a593Smuzhiyun }; 65