Lines Matching +full:0 +full:x1400
12 #clock-cells = <0>;
20 #clock-cells = <0>;
29 #clock-cells = <0>;
32 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
38 #clock-cells = <0>;
42 reg = <0x0d50>;
47 #clock-cells = <0>;
51 reg = <0x0b00>;
55 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
98 reg = <0x0b40>;
102 #clock-cells = <0>;
108 #clock-cells = <0>;
111 reg = <0x0b10>;
112 ti,bit-shift = <0>;
116 #clock-cells = <0>;
119 reg = <0x0a08>;
120 ti,bit-shift = <0>;
124 #clock-cells = <0>;
127 reg = <0x0a08>;
132 #clock-cells = <0>;
135 reg = <0x0a08>;
140 #clock-cells = <0>;
143 reg = <0x0a18>;
148 #clock-cells = <0>;
151 reg = <0x0a10>;
156 #clock-cells = <0>;
159 reg = <0x0a00>;
164 #clock-cells = <0>;
167 ti,bit-shift = <0>;
168 reg = <0x0e00>;
173 #clock-cells = <0>;
176 reg = <0x0e10>;
177 ti,bit-shift = <0>;
181 #clock-cells = <0>;
184 reg = <0x1400>;
189 #clock-cells = <0>;
192 reg = <0x1400>;
193 ti,bit-shift = <0>;
197 #clock-cells = <0>;
200 reg = <0x1410>;
201 ti,bit-shift = <0>;