Lines Matching +full:0 +full:x1400
59 printf("\n write reg 0x%08x = 0x%08x", addr, val); in dfs_reg_write()
77 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
118 u32 cs = 0; in ddr3_dfs_high_2_low()
124 freq_par = ddr3_get_freq_parameter(freq, 0); in ddr3_dfs_high_2_low()
134 /* [0] - DfsDllNextState - Disable */ in ddr3_dfs_high_2_low()
136 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
143 /* [0] - RetryMask - Disable */ in ddr3_dfs_high_2_low()
145 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
151 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
159 reg = (0x9 & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_high_2_low()
165 reg |= ((0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_high_2_low()
172 reg |= (0 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_high_2_low()
176 ~(0xF << REG_SDRAM_OPERATION_CS_OFFS)); in ddr3_dfs_high_2_low()
178 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
191 /* 0x16D0 - DDR3 Registered DRAM Control */ in ddr3_dfs_high_2_low()
196 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
209 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
214 } while (reg == 0x0); /* 0x1528 [3] - DfsAtSR - Wait for '1' */ in ddr3_dfs_high_2_low()
222 /* 0xE8264[7:0] 0xff CPU Clock Dividers Reset mask */ in ddr3_dfs_high_2_low()
223 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL0, (reg + 0xFF)); in ddr3_dfs_high_2_low()
228 /* 0xE8260 [15:8] 0x2 CPU Clock Dividers Reload Smooth enable */ in ddr3_dfs_high_2_low()
235 /* 0xE8260 [31:24] 0x2 Relax Enable */ in ddr3_dfs_high_2_low()
242 * 0xE8268 [13:8] N Set Training clock: in ddr3_dfs_high_2_low()
252 /* 0xE8264 [8]=0x1 CPU Clock Dividers Reload Ratio trigger set */ in ddr3_dfs_high_2_low()
261 /* 0xE8264 [8]=0x0 CPU Clock Dividers Reload Ratio trigger clear */ in ddr3_dfs_high_2_low()
270 * force reserved bits[7:0]. in ddr3_dfs_high_2_low()
272 reg = 0x0000FDFF; in ddr3_dfs_high_2_low()
273 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
280 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
281 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
289 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_high_2_low()
299 reg = 0x000FFF02; in ddr3_dfs_high_2_low()
312 * bits [7:0] == not in use in ddr3_dfs_high_2_low()
314 reg = 0x0102FDFF; in ddr3_dfs_high_2_low()
315 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
321 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_high_2_low()
322 * are active - 0x18718 [8] in ddr3_dfs_high_2_low()
327 } while (reg == 0); in ddr3_dfs_high_2_low()
333 reg = 0x000000FF; in ddr3_dfs_high_2_low()
334 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
345 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_high_2_low()
349 /* [15] - Phy2UnitClkRatio = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_high_2_low()
352 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_high_2_low()
358 /* 0x1404 - DDR Controller Control Low Register */ in ddr3_dfs_high_2_low()
366 reg |= (0x4 << REG_DFS_CL_NEXT_STATE_OFFS); in ddr3_dfs_high_2_low()
368 reg |= (0x1 << REG_DFS_CWL_NEXT_STATE_OFFS); in ddr3_dfs_high_2_low()
369 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
375 /* 0x1674 [10:0] - Phy lock status Register */ in ddr3_dfs_high_2_low()
380 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_high_2_low()
381 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
390 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
399 reg = (0xA & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_high_2_low()
406 reg |= ((0x0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_high_2_low()
410 reg |= (0x1 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_high_2_low()
414 ~(0xF << REG_SDRAM_OPERATION_CS_OFFS)); in ddr3_dfs_high_2_low()
416 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
429 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
432 * Poll - DFS Register - 0x1528 [3] - DfsAtSR - All DRAM devices in ddr3_dfs_high_2_low()
437 } while (reg); /* Wait for '0' */ in ddr3_dfs_high_2_low()
440 /* [3-0] = 0x2 - Refresh Command, [11-8] - enabled Cs */ in ddr3_dfs_high_2_low()
442 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
447 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
456 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
463 /* [0] - RetryMask - Enable */ in ddr3_dfs_high_2_low()
465 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
468 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
474 tmp = 0x4; /* CL=6 - 0x4 */ in ddr3_dfs_high_2_low()
475 reg |= ((tmp & 0x1) << REG_DDR3_MR0_CL_OFFS); in ddr3_dfs_high_2_low()
476 reg |= ((tmp & 0xE) << REG_DDR3_MR0_CL_HIGH_OFFS); in ddr3_dfs_high_2_low()
484 /* CWL=6 - 0x1 */ in ddr3_dfs_high_2_low()
485 reg |= ((0x1) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_high_2_low()
499 u32 cs = 0; in ddr3_dfs_high_2_low()
505 freq_par = ddr3_get_freq_parameter(freq, 0); in ddr3_dfs_high_2_low()
507 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
508 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
511 /* 0x1600 - ODPG_CNTRL_Control */ in ddr3_dfs_high_2_low()
517 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
519 reg &= REG_PHY_LOCK_MASK_MASK; /* [11:0] = 0 */ in ddr3_dfs_high_2_low()
522 reg = reg_read(REG_DFS_ADDR); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
525 reg &= ~0x10; /* [4] - Enable reconfig MR registers after DFS_ERG */ in ddr3_dfs_high_2_low()
526 reg |= 0x1; /* [0] - DRAM DLL disabled after DFS */ in ddr3_dfs_high_2_low()
528 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
530 reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); /* [0] - disable */ in ddr3_dfs_high_2_low()
531 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
536 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
540 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
543 * Poll DFS Register - 0x1528 [3] - DfsAtSR - in ddr3_dfs_high_2_low()
549 } while (reg == 0x0); /* Wait for '1' */ in ddr3_dfs_high_2_low()
555 /* [11:0] = 0 */ in ddr3_dfs_high_2_low()
557 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
566 * force reserved bits[7:0]. in ddr3_dfs_high_2_low()
568 reg = 0x0000FDFF; in ddr3_dfs_high_2_low()
569 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
575 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
576 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
583 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_high_2_low()
593 reg = 0x000FFF02; in ddr3_dfs_high_2_low()
606 * bits [7:0] == not in use in ddr3_dfs_high_2_low()
608 reg = 0x0102FDFF; in ddr3_dfs_high_2_low()
609 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
615 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_high_2_low()
616 * are active - 0x18718 [8] in ddr3_dfs_high_2_low()
621 } while (reg == 0); in ddr3_dfs_high_2_low()
627 reg = 0x000000FF; in ddr3_dfs_high_2_low()
628 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
634 reg = 0x20050000; in ddr3_dfs_high_2_low()
635 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_high_2_low()
639 /* [15] = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_high_2_low()
640 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Regist */ in ddr3_dfs_high_2_low()
644 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_high_2_low()
649 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_high_2_low()
654 /* 0x1404 */ in ddr3_dfs_high_2_low()
655 reg = (reg_read(REG_DUNIT_CTRL_LOW_ADDR) & 0xFFFFFFE7); in ddr3_dfs_high_2_low()
658 /* Poll Phy lock status register - APLL lock indication - 0x1674 */ in ddr3_dfs_high_2_low()
662 } while (reg != REG_PHY_LOCK_STATUS_LOCK_MASK); /* Wait for '0xFFF' */ in ddr3_dfs_high_2_low()
665 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_high_2_low()
666 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
671 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
676 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
683 reg &= ~0x74; /* CL [3:0]; [6:4],[2] */ in ddr3_dfs_high_2_low()
688 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
695 reg &= ~0x38; /* CWL [5:3] */ in ddr3_dfs_high_2_low()
701 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
725 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
729 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
732 * Poll DFS Register - 0x1528 [3] - DfsAtSR - in ddr3_dfs_high_2_low()
740 reg = (reg_read(REG_METAL_MASK_ADDR) | (1 << 0)); in ddr3_dfs_high_2_low()
741 /* [0] - Enable Dunit to crossbar retry */ in ddr3_dfs_high_2_low()
742 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
745 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_high_2_low()
747 reg &= ~(1 << REG_ODPG_CNTRL_OFFS); /* [21] = 0 */ in ddr3_dfs_high_2_low()
750 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
752 reg |= ~REG_PHY_LOCK_MASK_MASK; /* [11:0] = FFF */ in ddr3_dfs_high_2_low()
774 u32 cs = 0; in ddr3_dfs_low_2_high()
790 /* [0] - DfsDllNextState - Enable */ in ddr3_dfs_low_2_high()
792 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
799 /* [0] - RetryMask - Disable */ in ddr3_dfs_low_2_high()
801 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
807 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
812 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
817 } while (reg == 0x0); /* 0x1528 [3] - DfsAtSR - Wait for '1' */ in ddr3_dfs_low_2_high()
825 /* 0xE8264[7:0] 0xff CPU Clock Dividers Reset mask */ in ddr3_dfs_low_2_high()
826 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL0, (reg + 0xFF)); in ddr3_dfs_low_2_high()
831 /* 0xE8260 [15:8] 0x2 CPU Clock Dividers Reload Smooth enable */ in ddr3_dfs_low_2_high()
838 /* 0xE8260 [31:24] 0x2 Relax Enable */ in ddr3_dfs_low_2_high()
845 * 0xE8268 [13:8] N Set Training clock: in ddr3_dfs_low_2_high()
854 /* 0xE8264 [8]=0x1 CPU Clock Dividers Reload Ratio trigger set */ in ddr3_dfs_low_2_high()
863 /* 0xE8264 [8]=0x0 CPU Clock Dividers Reload Ratio trigger clear */ in ddr3_dfs_low_2_high()
872 * and force reserved bits[7:0]. in ddr3_dfs_low_2_high()
874 reg = 0x0000FFFF; in ddr3_dfs_low_2_high()
876 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
882 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
883 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
890 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_low_2_high()
898 reg = 0x000FFF02; in ddr3_dfs_low_2_high()
904 reg = 0x0102FDFF; in ddr3_dfs_low_2_high()
912 * bits [7:0] == not in use in ddr3_dfs_low_2_high()
914 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
920 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_low_2_high()
921 * are active - 0x18718 [8] in ddr3_dfs_low_2_high()
926 } while (reg == 0); in ddr3_dfs_low_2_high()
928 reg = 0x000000FF; in ddr3_dfs_low_2_high()
933 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
943 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_low_2_high()
960 * [15] - Phy2UnitClkRatio = 0 - Set 1:1 Ratio between in ddr3_dfs_low_2_high()
966 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_low_2_high()
974 /* 0x1404 - DDR Controller Control Low Register */ in ddr3_dfs_low_2_high()
983 if (dram_info->target_frequency == 0x8) in ddr3_dfs_low_2_high()
995 reg |= (((0) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()
1002 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1005 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1019 /* 0x15EC - DRAM PHY Config Register */ in ddr3_dfs_low_2_high()
1025 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_low_2_high()
1032 /* 0x1674 [10:0] - Phy lock status Register */ in ddr3_dfs_low_2_high()
1038 /* [28] - DataPupRdRST = 0 */ in ddr3_dfs_low_2_high()
1044 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1048 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1054 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_low_2_high()
1055 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1064 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1073 reg = (0xA & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_low_2_high()
1080 reg |= ((0x0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1087 reg |= ((0x1 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1094 reg |= ((0x2 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1101 reg |= ((0x3 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1106 reg |= (0x1 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_low_2_high()
1109 ~(0xF << REG_SDRAM_OPERATION_CS_OFFS)); in ddr3_dfs_low_2_high()
1111 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1124 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1127 * Poll - DFS Register - 0x1528 [3] - DfsAtSR - All DRAM in ddr3_dfs_low_2_high()
1132 } while (reg); /* Wait for '0' */ in ddr3_dfs_low_2_high()
1135 /* [3-0] = 0x2 - Refresh Command, [11-8] - enabled Cs */ in ddr3_dfs_low_2_high()
1137 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1142 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1151 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1158 /* [0] - RetryMask - Enable */ in ddr3_dfs_low_2_high()
1160 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
1163 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1173 reg |= ((tmp & 0x1) << REG_DDR3_MR0_CL_OFFS); in ddr3_dfs_low_2_high()
1174 reg |= ((tmp & 0xE) << REG_DDR3_MR0_CL_HIGH_OFFS); in ddr3_dfs_low_2_high()
1183 reg |= ((0) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
1201 u32 cs = 0; in ddr3_dfs_low_2_high()
1209 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
1212 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1217 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1219 reg &= REG_PHY_LOCK_MASK_MASK; /* [11:0] = 0 */ in ddr3_dfs_low_2_high()
1223 reg = reg_read(REG_DFS_ADDR); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1225 reg &= ~0x11; in ddr3_dfs_low_2_high()
1226 /* [0] - Enable - DRAM DLL after DFS */ in ddr3_dfs_low_2_high()
1227 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1230 /* [0] - disable */ in ddr3_dfs_low_2_high()
1231 reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); in ddr3_dfs_low_2_high()
1232 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
1238 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1243 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1249 /* 0x1528 [3] - DfsAtSR */ in ddr3_dfs_low_2_high()
1252 } while (reg == 0x0); /* Wait for '1' */ in ddr3_dfs_low_2_high()
1263 /* [15] = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_low_2_high()
1267 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_low_2_high()
1269 /* Switch HCLK Mux from (100Mhz) [16]=0, keep DFS request bit */ in ddr3_dfs_low_2_high()
1270 reg = 0x20040000; in ddr3_dfs_low_2_high()
1276 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_low_2_high()
1285 * force reserved bits[7:0]. in ddr3_dfs_low_2_high()
1287 reg = 0x0000FFFF; in ddr3_dfs_low_2_high()
1288 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
1294 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
1295 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
1302 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_low_2_high()
1311 reg = 0x000FFF02; in ddr3_dfs_low_2_high()
1318 reg = 0x0102FDFF; in ddr3_dfs_low_2_high()
1326 * bits [7:0] == not in use in ddr3_dfs_low_2_high()
1328 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
1334 * Poll Div CLK status 0 register - indication that the clocks are in ddr3_dfs_low_2_high()
1335 * active - 0x18718 [8] in ddr3_dfs_low_2_high()
1340 } while (reg == 0); in ddr3_dfs_low_2_high()
1342 reg = 0x000000FF; in ddr3_dfs_low_2_high()
1347 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
1354 /* [28] = 0 - Pup Reset Divider B */ in ddr3_dfs_low_2_high()
1358 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1362 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1369 /* 0x15EC - DRAM PHY Config Register */ in ddr3_dfs_low_2_high()
1374 /* APLL lock indication - Poll Phy lock status Register - 0x1674 [9] */ in ddr3_dfs_low_2_high()
1378 } while (reg == 0); in ddr3_dfs_low_2_high()
1383 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_low_2_high()
1389 * APLL lock indication - Poll Phy lock status Register - 0x1674 [11:0] in ddr3_dfs_low_2_high()
1398 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_low_2_high()
1399 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1405 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1410 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1414 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1417 * Poll DFS Register - 0x1528 [3] - DfsAtSR - All DRAM devices on in ddr3_dfs_low_2_high()
1422 } while (reg); /* Wait for '0' */ in ddr3_dfs_low_2_high()
1424 /* 0x1404 */ in ddr3_dfs_low_2_high()
1425 reg = (reg_read(REG_DUNIT_CTRL_LOW_ADDR) & 0xFFFFFFE7) | 0x2; in ddr3_dfs_low_2_high()
1436 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1447 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_dfs_low_2_high()
1450 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1464 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_dfs_low_2_high()
1467 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1474 reg &= ~0x74; /* CL [3:0]; [6:4],[2] */ in ddr3_dfs_low_2_high()
1477 tmp = ddr3_cl_to_valid_cl(6) & 0xF; in ddr3_dfs_low_2_high()
1479 tmp = ddr3_cl_to_valid_cl(dram_info->cl) & 0xF; in ddr3_dfs_low_2_high()
1481 reg |= ((tmp & 0x1) << 2); in ddr3_dfs_low_2_high()
1487 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1494 reg &= ~0x38; /* CWL [5:3] */ in ddr3_dfs_low_2_high()
1495 /* CWL = 0 ,for 400 MHg is 5 */ in ddr3_dfs_low_2_high()
1501 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1526 dfs_reg_write(REG_SDRAM_ODT_CTRL_HIGH_ADDR, 0); in ddr3_dfs_low_2_high()
1530 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1533 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1535 reg &= ~(1 << REG_ODPG_CNTRL_OFFS); /* [21] = 0 */ in ddr3_dfs_low_2_high()
1539 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1541 reg |= ~REG_PHY_LOCK_MASK_MASK; /* [11:0] = FFF */ in ddr3_dfs_low_2_high()
1544 reg = reg_read(REG_METAL_MASK_ADDR) | (1 << 0); /* [0] - disable */ in ddr3_dfs_low_2_high()
1545 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()